Automated extraction of accurate delay/timing macromodels of digital gates and latches using trajectory piecewise methods

Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC

Volumn , Issue , 2007, Pages 361-366

  Dabas, Sandeep ^a   Dong, Ning ^b   Roychowdhury, Jaijeet ^a  

^a UNIVERSITY OF MINNESOTA   (United States)

^b TEXAS INSTRUMENTS   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

ACCURATE DELAY MODELS; AUTOMATED EXTRACTION; CASCADE (CO); CURRENT SOURCE (CS); DESIGN AUTOMATION CONFERENCE (DAC); DESIGN STYLES; DIGITAL GATES; FULL ADDER (FA); GATE DELAYS; INTERNAL STATES; MACRO-MODELS; MODEL ACCURACY; MULTI INPUT; MULTIPLE-INPUT SWITCHING; NANOSCALE TECHNOLOGIES; NEW APPROACHES; SOUTH PACIFIC; WAVE FORMS; XOR GATES;

ADDERS; CELLULAR RADIO SYSTEMS; COMPUTER AIDED DESIGN; DIGITAL ARITHMETIC; DIGITAL INTEGRATED CIRCUITS; EXTRACTION; INDUSTRIAL ENGINEERING; MECHANIZATION; NANOTECHNOLOGY; SPICE; TRAJECTORIES;

AUTOMATION;

EID: 38649123442     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ASPDAC.2007.358012     Document Type: Conference Paper

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