Configurable multi-layer CNN-UM emulator on FPGA using distributed arithmetic

Proceedings of the IEEE International Conference on Electronics, Circuits, and Systems

Volumn 3, Issue , 2002, Pages 1251-1254

  Nagy, Zoltán ^a   Szolgay, Péter ^a  

^a UNIVERSITY OF PANNONIA   (Hungary)

Author keywords

[No Author keywords available]

Indexed keywords

ADDER TREE; ARITHMETIC UNIT; CHIP ARCHITECTURE; COMPUTING POWER; CONFIGURABLE; CONVENTIONAL APPROACH; DISTRIBUTED ARITHMETIC; DISTRIBUTED ARITHMETIC TECHNIQUES; FPGA IMPLEMENTATIONS; PROCESSOR ARRAY; REAL-TIME IMAGE PROCESSING; RUNTIMES; SOFTWARE SIMULATION; STATE EQUATIONS;

EQUATIONS OF STATE; FILTER BANKS; IMAGE PROCESSING; OPTIMIZATION;

COMPUTER SOFTWARE;

EID: 38649091426     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ICECS.2002.1046481     Document Type: Conference Paper

References (8)

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