Performance/energy optimization of DSP transforms on the XScale processor

Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics)

Volumn 4367 LNCS, Issue , 2007, Pages 201-214

  D'Alberto, Paolo ^a   Püschel, Markus ^a   Franchetti, Franz ^a  

^a CARNEGIE MELLON UNIVERSITY   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

DISCRETE FOURIER TRANSFORMS; MICROPROCESSOR CHIPS; NATURAL FREQUENCIES; OPTIMIZATION; PROBLEM SOLVING; SIGNAL PROCESSING;

PROBLEM SIZE; WALSH HADAMARD TRANSFORM (WHT); XSCALE PROCESSOR;

ENERGY MANAGEMENT;

EID: 38149136433     PISSN: 03029743     EISSN: 16113349     Source Type: Book Series    
DOI: 10.1007/978-3-540-69338-3_14     Document Type: Conference Paper

References (14)

1. Püschel, M., Moura, J.M.F., Johnson, J., Padua, D., Veloso, M., Singer, B.W., Xiong, J., Franchetti, F., Gačić, A., Voronenko, Y., Chen, K., Johnson, R.W., Rizzolo, N.: SPIRAL: Code generation for DSP transforms. Proc. of the IEEE 93(2) (2005) 232-275 Special issue on Program Generation, Optimization, and Adaptation.
2. Halambi, A., Shrivastava, A., Dutt, N., Nicolau, A.: A customizable compiler framework for embedded systems. In: Proc. Workshop on Software and Compilers for Embedded Systems. (2001)
3. Contreras, G., Martonosi, M.: Power prediction for Intel XScale processors using performance monitoring unit events. In: Proc. International Symposium on Low Power Electronics and Design (ISLPED). (2005) 221-226
4. Singleton, L., Poellabauer, C., Schwan, K.: Monitoring of cache miss rates for accurate dynamic voltage and frequency scaling. In: Proc. Multimedia Computing and Networking Conference. (2005)
5. Hsu, C., Kremer, U.: The design, implementation, and evaluation of a compiler algorithm for CPU energy reduction. In: Proc. Conference on Programming Language Design and Implementation (PLDI). (2003) 38-48
6. Xie, F., Martonosi, M., Malik, S.: Compile-time dynamic voltage scaling settings: Opportunities and limits. In: Proc. Conference on Programming Language Design and Implementation (PLDI). (2003) 49-62
7. Whaley, R.C., Petitet, A., Dongarra, J.J.: Automated empirical optimization of software and the ATLAS project. Parallel Computing 27(1-2) (2001) 3-35
8. Im, E.J., Yelick, K., Vuduc, R.: Sparsity: Optimization framework for sparse matrix kernels. Int'l J. High Performance Computing Applications 18(1) (2004)
9. Frigo, M., Johnson, S.G.: The design and implementation of FFTW3. Proc. of the IEEE 93(2) (2005) 216-231 Special issue on Program Generation, Optimization, and Adaptation.
10. Intel: Intel XScale Microarchitecture. (2001)
11. Van Loan, C.: Computational Framework of the Fast Fourier Transform. SIAM (1992)
12. Gačić, A., Pilschel, M., Moura, J.M.F.: Fast automatic implementations of FIR filters. In: Proc. International Conference on Acoustics, Speech, and Signal Processing (ICASSP). Volume 2. (2003) 541-544
13. Gačić, A.: Automatic Implementation and Platform Adaptation of Discrete Filtering and Wavelet Algorithms. PhD thesis, Electrical and Computer Engineering, Carnegie Mellon University (2004)
14. Franchetti, F., Voronenko, Y., Pilschel, M.: Loop merging for signal transforms. In: Proc. Programming Language Design and Implementation (PLDI). (2005) 315-326