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Volumn 4367 LNCS, Issue , 2007, Pages 183-197

Efficient program power behavior characterization

Author keywords

[No Author keywords available]

Indexed keywords

CLASSIFICATION (OF INFORMATION); COMPUTER SIMULATION; OPTIMIZATION; PROGRAM COMPILERS; VECTORS;

EID: 38149041617     PISSN: 03029743     EISSN: 16113349     Source Type: Book Series    
DOI: 10.1007/978-3-540-69338-3_13     Document Type: Conference Paper
Times cited : (6)

References (20)
  • 5
    • 84932083885 scopus 로고    scopus 로고
    • Eliminating voltage emergencies via microarchitectural voltage control feedback and dynamic optimization
    • Newport Beach, CA, August
    • K. Hazelwood and D. Brooks. Eliminating voltage emergencies via microarchitectural voltage control feedback and dynamic optimization. In International Symposium on Low-Power Electronics and Design, Newport Beach, CA, August 2004.
    • (2004) International Symposium on Low-Power Electronics and Design
    • Hazelwood, K.1    Brooks, D.2
  • 10
    • 33748856569 scopus 로고    scopus 로고
    • C. Isci and M. Martonosi. Phase characterization for power: Evaluating control-flow-based and event-counter-based techniques. In 12th International Symposium on High-Performance Computer Architecture (HPCA-12), Febrary 2006.
    • C. Isci and M. Martonosi. Phase characterization for power: Evaluating control-flow-based and event-counter-based techniques. In 12th International Symposium on High-Performance Computer Architecture (HPCA-12), Febrary 2006.
  • 12
    • 33744504206 scopus 로고    scopus 로고
    • J. Lau, E. Perelman, G. Hamerly, T. Sherwood, and B. Calder. Motivation for variable length intervals and hierarchical phase behavior. In the Proceedings of the IEEE International Symposium on Performance Analysis of Systems and Software (ISPASS'05), pages 135-146, 2005.
    • J. Lau, E. Perelman, G. Hamerly, T. Sherwood, and B. Calder. Motivation for variable length intervals and hierarchical phase behavior. In the Proceedings of the IEEE International Symposium on Performance Analysis of Systems and Software (ISPASS'05), pages 135-146, 2005.
  • 18
    • 0003147684 scopus 로고
    • Low power architecture and compilation techniques for high-performance processors
    • San Francisco, CA, February
    • C.-L. Su, C.-Y. Tsui, and A. Despain. Low power architecture and compilation techniques for high-performance processors. In IEEE COMPCON, pages 489-498, San Francisco, CA, February 1994.
    • (1994) IEEE COMPCON , pp. 489-498
    • Su, C.-L.1    Tsui, C.-Y.2    Despain, A.3
  • 19
    • 0004001433 scopus 로고    scopus 로고
    • Instruction scheduling for low power dissipation in high performance microprocessors
    • Barcelona, Spain, June
    • M. Toburen, T. Conte, and M. Reilly. Instruction scheduling for low power dissipation in high performance microprocessors. In Power Driven Microarchitecture Workshop, Barcelona, Spain, June 1998.
    • (1998) Power Driven Microarchitecture Workshop
    • Toburen, M.1    Conte, T.2    Reilly, M.3


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.