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Volumn 4808 LNCS, Issue , 2007, Pages 1-12

Real-time loop scheduling with energy optimization via DVS and ABB for multi-core embedded system

Author keywords

[No Author keywords available]

Indexed keywords

ADAPTIVE SYSTEMS; CONSTRAINT THEORY; ENERGY UTILIZATION; OPTIMIZATION; SCHEDULING;

EID: 38149039432     PISSN: 03029743     EISSN: 16113349     Source Type: Book Series    
DOI: 10.1007/978-3-540-77092-3_1     Document Type: Conference Paper
Times cited : (10)

References (14)
  • 1
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    • Andrei, A., Schmitz, M., Eles, P., Peng, Z., Al-Hashimi, B.: Overhead-conscious voltage selection for dynamic and leakage power reduction of time-constraint systems. In: DATE 2004, pp. 518-523 (2004)
    • Andrei, A., Schmitz, M., Eles, P., Peng, Z., Al-Hashimi, B.: Overhead-conscious voltage selection for dynamic and leakage power reduction of time-constraint systems. In: DATE 2004, pp. 518-523 (2004)
  • 2
    • 16244423681 scopus 로고    scopus 로고
    • Andrei, A., Schmitz, M., Eles, P., Peng, Z., Al-Hashimi, B.: Simultaneous communication and processor voltage scaling for dynamic and leakage energy reduction in time-constrained systems. In: DATE 2004, pp. 362-369 (2004)
    • Andrei, A., Schmitz, M., Eles, P., Peng, Z., Al-Hashimi, B.: Simultaneous communication and processor voltage scaling for dynamic and leakage energy reduction in time-constrained systems. In: DATE 2004, pp. 362-369 (2004)
  • 4
    • 0031097278 scopus 로고    scopus 로고
    • Rotation scheduling: A loop pipelining algorithm
    • Chao, L.-F., LaPaugh, A.S., Sha, E.H.-M.: Rotation scheduling: A loop pipelining algorithm. TCAD 16(3), 229-239 (1997)
    • (1997) TCAD , vol.16 , Issue.3 , pp. 229-239
    • Chao, L.-F.1    LaPaugh, A.S.2    Sha, E.H.-M.3
  • 6
    • 34047189294 scopus 로고    scopus 로고
    • Huang, P., Ghiasi, S.: Power-aware compilation for embedded processors with dynamic voltage scaling and adaptive body biasing capabilities. In: DATE 2006, pp. 943-944 (2006)
    • Huang, P., Ghiasi, S.: Power-aware compilation for embedded processors with dynamic voltage scaling and adaptive body biasing capabilities. In: DATE 2006, pp. 943-944 (2006)
  • 7
    • 38149088185 scopus 로고    scopus 로고
    • Intel. IA-32 Intel Architecture Optimization Reference Manual (April 2006)
    • Intel. IA-32 Intel Architecture Optimization Reference Manual (April 2006)
  • 9
    • 0036917242 scopus 로고    scopus 로고
    • Combined dynamic voltage scaling and adaptive body biasing for lower power microprocessors under dynamic workloads
    • Martin, S., Flautner, K., Mudge, T., Blaauw, D.: Combined dynamic voltage scaling and adaptive body biasing for lower power microprocessors under dynamic workloads. In: ICCAD 2002, pp. 721-725 (2002)
    • (2002) ICCAD 2002 , pp. 721-725
    • Martin, S.1    Flautner, K.2    Mudge, T.3    Blaauw, D.4
  • 10
    • 0036974702 scopus 로고    scopus 로고
    • Energy-conscious compilation based on voltage sacling
    • Saputra, H., Kandemir, M.: Energy-conscious compilation based on voltage sacling. In: LCTES 2002 (2002)
    • (2002) LCTES
    • Saputra, H.1    Kandemir, M.2
  • 11
    • 38149142691 scopus 로고    scopus 로고
    • Shao, Z., Wang, M., Chen, Y., Xue, C., Qiu, M., Yang, L.T., Sha, E.H.-M.: Real-time dynamic voltage loop scheduling for multi-core embedded systems. Accepted in IEEE Transactions on Circuits and Systems II (TCAS-II)
    • Shao, Z., Wang, M., Chen, Y., Xue, C., Qiu, M., Yang, L.T., Sha, E.H.-M.: Real-time dynamic voltage loop scheduling for multi-core embedded systems. Accepted in IEEE Transactions on Circuits and Systems II (TCAS-II)
  • 12
    • 0021477994 scopus 로고
    • Short-circuit dissipation of static cmos circuitry and its impact on the design of buffer circuits
    • Veendrick, H.: Short-circuit dissipation of static cmos circuitry and its impact on the design of buffer circuits. IEEE J. Solid-State Circuits 19, 468-473 (1984)
    • (1984) IEEE J. Solid-State Circuits , vol.19 , pp. 468-473
    • Veendrick, H.1
  • 13
    • 22544455956 scopus 로고    scopus 로고
    • Joint dynamic voltage scaling and adaptive body biasing for heterogeneous distributed real-time embedded systems
    • Yan, L., Luo, .J., Jha, N.K.: Joint dynamic voltage scaling and adaptive body biasing for heterogeneous distributed real-time embedded systems. TCAD 24(7), 1030-1041 (2005)
    • (2005) TCAD , vol.24 , Issue.7 , pp. 1030-1041
    • Yan, L.1    Luo, J.2    Jha, N.K.3
  • 14
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    • Code size reduction technique and implementation for software-pipelined dsp applications
    • Zhuge, Q., Xiao. B., Sha. E.H.-M.: Code size reduction technique and implementation for software-pipelined dsp applications. TECS 2(4), 1-24 (2003)
    • (2003) TECS , vol.2 , Issue.4 , pp. 1-24
    • Zhuge, Q.1    Xiao, B.2    Sha, E.H.-M.3


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.