Evaluation of the masked logic style MDPL on a prototype chip

Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics)

Volumn 4727 LNCS, Issue , 2007, Pages 81-94

  Popp, Thomas ^a   Kirschbaum, Mario ^a   Zefferer, Thomas ^a   Mangard, Stefan ^b  

^a GRAZ UNIVERSITY OF TECHNOLOGY   (Austria)

^b INFINEON TECHNOLOGIES AG   (Germany)

Author keywords

DPA resistant logic styles; Dual rail precharge logic; Early propagation effect; Improved MDPL; Masked logic; Prototype chip

Indexed keywords

ELECTRIC POWER UTILIZATION; MICROCONTROLLERS; PROBLEM SOLVING; SECURITY OF DATA;

DUAL RAIL PRECHARGE LOGIC; EARLY PROPAGATION EFFECTS; MASKED LOGIC; PROTOTYPE CHIPS;

FORMAL LOGIC;

EID: 38049043381     PISSN: 03029743     EISSN: 16113349     Source Type: Book Series    
DOI: 10.1007/978-3-540-74735-2_6     Document Type: Conference Paper

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