A new duty cycle control strategy for power factor correction and FPGA implementation

IEEE Transactions on Power Electronics

Volumn 21, Issue 6, 2006, Pages 1745-1753

  Zhang, Wanfeng ^a,b   Liu, Yan Fei ^a   Wu, Bin ^c  

^a QUEEN S UNIVERSITY   (Canada)

^b Solar Semiconductor Inc   (United States)

^c RYERSON UNIVERSITY   (Canada)

Author keywords

Field programmable gate array (FPGA); Power factor correction (PFC); Switched mode power supplies (SMPS)

Indexed keywords

ALGORITHMS; ELECTRIC CURRENTS; ELECTRIC INDUCTORS; ELECTRIC POTENTIAL; FIELD PROGRAMMABLE GATE ARRAYS;

DUTY CYCLE CONTROL; POWER FACTOR CORRECTION; SWITCHED MODE POWER SUPPLIES;

POWER ELECTRONICS;

EID: 37849186319     PISSN: 08858993     EISSN: None     Source Type: Journal    
DOI: 10.1109/TPEL.2006.882922     Document Type: Article

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