Design and analysis of a layer seven network processor accelerator using reconfigurable logic

IEEE Symposium on FPGAs for Custom Computing Machines, Proceedings

Volumn 2002-January, Issue , 2002, Pages 131-142

  Memik, Gokhan ^a   Memik, Seda Ogrenci ^b   Mangione Smith, William H ^a  

^a UNIVERSITY OF CALIFORNIA   (United States)

^b University of California   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

ALGORITHMS; COMPUTATION THEORY; COMPUTERS; FIELD PROGRAMMABLE GATE ARRAYS (FPGA); INTEGRATED CIRCUIT DESIGN; NETWORK LAYERS; PATTERN MATCHING;

DESIGN AND ANALYSIS; FPGA IMPLEMENTATIONS; IMPROVE PERFORMANCE; NETWORK PROCESSING APPLICATIONS; NETWORK PROCESSOR; NETWORKING APPLICATIONS; RECONFIGURABLE LOGIC; RECONFIGURATION TIME;

ACCELERATION;

EID: 37249075916     PISSN: 10823409     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/FPGA.2002.1106668     Document Type: Conference Paper

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