Phase-aware adaptive hardware selection for power-efficient scientific computations

Proceedings of the International Symposium on Low Power Electronics and Design

Volumn , Issue , 2007, Pages 403-406

  Malkowski, Konrad ^a   Raghavan, Padma ^a   Kandemir, Mahmut ^a   Irwin, Mary Jane ^a  

^a The Pennsylvania State University   (United States)

Author keywords

DVFS adaptive architecture prefetchers sparse scientific codes performance power energy

Indexed keywords

DYNAMIC VOLTAGE SCALING; FREQUENCY SCALING; HIGH PERFORMANCE COMPUTING (HPC); MEMORY BOUND PHASES; UNOPTIMIZED SYSTEM;

COMPUTATION THEORY; ELECTRIC POWER UTILIZATION; HEAT LOSSES;

NATURAL SCIENCES COMPUTING;

EID: 36949014036     PISSN: 15334678     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1145/1283780.1283869     Document Type: Conference Paper

References (14)

1. P. Gelsinger. GigaScale integration for teraops performance - challenges, opportunities, and new frontiers, 2004. DAC 2004 Keynote. Talk and slides at http://www.dac.com.
2. G. Chen, K. Malkowski, M. Kandemir, and P. Raghavan. Reducing power with performance constraints for parallel sparse applications. In Parallel and Distributed Processing Symposium, 2005. Proceedings. 19th IEEE International, pages 8 pp.-, April 2005.
3. C.-H. Hsu and W.-C. Feng. A power-aware run-time system for high-performance computing. In SC '05: Proceedings of the 2005 ACM/IEEE conference on Supercomputing, page 1, Washington, DC, USA, 2005. IEEE Computer Society.
4. K. Malkowski, I. Lee, P. Raghavan, and M.J. Irwin. Conjugate gradient sparse solvers: Performance-power characteri sties. In Proceedings of the 20th IEEE International Parallel and Distributed Symposium, IPDPS'06, Second High-Performance, Power-Aware Computing Workshop, April 2006.
5. K. Choi, R. Soma, and M. Pedram. Dynamic voltage and frequency scaling based on workload decomposition. In ISLPED '04: Proceedings of the 2004 international symposium on Low power electronics and design, pages 174-179, New York, NY, USA, 2004. ACM Press.
6. D. Burger and T. M. Austin. The SimpleScalar tool set, version 2.0. SIGARCH Comput. Archit. News, 25(3): 13-25, 1997.
7. D. Brooks, V Tiwari, and M. Martonosi. Wattch: a framework for architectural-level power analysis and optimizations. In ISCA '00: Proceedings of the 27th annual international symposium on Computer architecture, pages 83-94. ACM Press, 2000.
8. W. D. Gropp, D. K. Kaushik, D. E. Keyes, and B. F. Smith. Performance modeling and tuning of an unstructured mesh CFD application. In Proceedings of SC2000. IEEE Computer Society, 2000.
9. D. H. Bailey, L. Dagum, E. Barszcz, and H. D. Simon. NAS parallel benchmark results. In Supercomputing '92: Proceedings of the 1992 ACM/IEEE conference on Supercomputing, pages 386-393, Los Alamitos, CA, USA, 1992. IEEE Computer Society Press.
10. Y. Saad. Iterative Methods for Sparse Linears Systems. PWS Publishing Co., Boston, MA, 1996.
11. E. Perelman, G. Hamerly, M. Van Biesbrouck, T. Sherwood, and. B. Calder. Using simpoint for accurate and efficient simulation. In SIGMETRICS '03: Proceedings of the 2003 ACM SIGMETRICS international conference on Measurement and modeling of computer systems, pages 318-319, New York, NY, USA, 2003. ACM Press.
12. N. Kappiah, V.W. Freeh, and D.K. Lowenthal. Just in time dynamic voltage scaling: Exploiting inter-node slack to save energy in mpi programs. In Supercomputing, 2005. Proceedings of the ACM/IEEE SC 2005 Conference, vol., no.pp. 33- 33, Nov. 2005.
13. S. Borkar. Design challenges of technology scaling. IEEE Micro, 19(4):23-29, 1999.
14. C Isci, G. Contreras, and M. Martonosi. Live, runtime phase monitoring and prediction on real systems with, application to dynamic power management. In MICRO '06: Proceedings of the 39th Annual IEEE/ACM International Symposium on Microarchitecture, pages 359-370, Washington, DC, USA, 2006. IEEE Computer Society.