Implementation of a parallel and pipelined watershed algorithm on FPGA

Proceedings - 2006 International Conference on Field Programmable Logic and Applications, FPL

Volumn , Issue , 2006, Pages 561-566

  Trieu, Dang Ba Khac ^a   Maruyama, Tsutomu ^a  

^a UNIVERSITY OF TSUKUBA   (Japan)

Author keywords

[No Author keywords available]

Indexed keywords

BOOLEAN FUNCTIONS; FIELD PROGRAMMABLE GATE ARRAYS (FPGA); FUZZY LOGIC; LANDFORMS; PARALLEL ALGORITHMS; WATERSHEDS;

APPLIED (CO); EXTERNAL MEMORIES; FIELD PROGRAMMABLE LOGIC (FPL); HIGH PERFORMANCE; IN ORDER; INTERNATIONAL CONFERENCES; LOADING TIME; MEMORY ACCESSES; PIXEL IMAGES; REAL-TIME APPLICATIONS; STORE IMAGE; WATERSHED ALGORITHMS;

PIXELS;

EID: 36949004638     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/FPL.2006.311267     Document Type: Conference Paper

References (7)

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4. H. Sun, J. Yang, M. Ren, "A fast watershed algorithm based on chain code and its application in image segmentation", Pattern Recognition Letters 26 (2005) 1266-1274.
5. Zahirazami, Shahram Akil, Mohamed, "Implementation of a watershed algorithm on FPGAs", Proc. SPIE Applications of Digital Image Processing, Vol. 3460, p. 98-105, 1999.
6. Kumud P. Gupta, S. Srinivasan, "Reduced Memory Implementation of Modified Serial Watershed Algorithm Based Ordered Queue", International Conference on Information Technology: Computers and Communications (ITCC) 2003
7. Rambabu, C. Chakrabarti, I. Mahanta, A., "Flooding-based watershed algorithm and its prototype hardware architecture", Vision, Image and Signal Processing, IEE, Vol. 151 (3), 2004