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1
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36749086694
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Tevatron Run II Handbook 〈http://www-bd.fnal.gov/lug/〉.
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3
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36749047119
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The Tevatron Run II Upgrade Project 〈http://www-bd.fnal.gov/run2upgrade/〉.
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8
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36749062133
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The right-handed D0 coordinate system is defined with the z-axis in the direction of the proton beam, with φ measuring the azimuthal angle in the plane transverse to the beam direction, with θ measuring the polar angle, and with the pseudo-rapidity, η = - ln [tan (θ / 2)].
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10
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36749083710
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See for example: The ATLAS Level-1 Trigger Group, ATLAS Level-1 Trigger Technical Design Report 〈http://atlas.web.cern.ch/Atlas/GROUPS/DAQTRIG/TDR/tdr.html〉 ATLAS TDR-12, 1998; The CMS Collaboration, The TriDAS Project Technical Design Report, vol. 1: The Trigger Systems 〈http://cmsdoc.cern.ch/cms/TDR/TRIGGER-public/trigger.html〉, CERN/LHCC 2000-38, 2000; J. Alitti, et al., Z. Phys. C 49 (1991) 17.
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11
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36749051151
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The D0 collaboration, Run IIb Upgrade Technical Design Report, Fermilab-Pub-02/327-E, 2002.
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12
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36749039971
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WIENER, Plein & Bauss Ltd 〈http://www.wiener-us.com/〉.
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13
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36749057526
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3M Corporation, Pleated foil shielded cable (90211 Series) 〈http://www.3m.com〉.
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14
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36749099685
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Analog Devices, 10-Bit 40 MSPS 3 V Dual A/D Converter (AD9218BST-40) 〈http://www.analog.com〉.
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15
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36749065790
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Xilinx, Virtex-II FPGA (XC2V1000-4FG456C) 〈http://www.xilinx.com/〉.
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16
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36749014217
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National Semiconductor, 48-bit Channel Link SER/DES(DS90CR483/4) 〈http://www.national.com〉.
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17
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36749036899
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W.L. Gore & Associates, Inc., Eye-Opener Millipacs 2/Z-Pack 2 mm HM Cable Connector (2MMS02xx) 〈http://www.gore.com〉.
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18
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36749059733
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Altera, Stratix Device Family (EP1Sxx) 〈http://www.altera.com〉 (EP1S20F780C7, EP1S20F780C6, EP1S10F780C6, and EP1S30F1020C6 devices are used for the TAB SWA, TAB global, GAB LVDS and GAB S30 FPGAs, respectively).
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19
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36749051989
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Agilent Technologies, Transmit/Receive Chip Set (HDMP-1022) 〈http://www.agilent.com〉; Stratos Optical Technologies, Optical Gbit Dual Transmitter (M2T-25-4-1-L) 〈http://www.stratoslightwave.com〉.
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20
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36749008208
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Altera, Cyclone Device Family (EP1C6Q240C7) 〈http://www.altera.com〉.
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21
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36749065789
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Altera, Serial Configuration Device (EPCS4SI8) 〈http://www.altera.com〉.
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22
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36749103418
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Cypress Semiconductor Corporation, Clock Distribution Buffer (CY29948AI) 〈http://www.altera.com〉.
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23
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36749001302
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Fairchild Semiconductor, TTL to ECL Converter (FDLL4148) 〈http://www.fairchildsemi.com〉.
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24
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36749054274
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National Semiconductor, Differential Line Drivers/Receivers (DS90LV047/8 ATMTC) 〈http://www.national.com〉.
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25
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36749094821
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As currently implemented the North, Central and South regions correspond to 3.2 < η < 1.0, 1.0 < η < - 1.0, and - 1.0 < η < 3.2, respectively.
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26
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36749010445
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Altera, ACEX 1K Series FPGA (EP1K50QC208-2) 〈http://www.altera.com〉.
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27
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36748999645
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Because of the extra latency involved in the divide operation necessary for the calculation of the Tau algorithm isolation, this information is not available in time for transmission to the L1CalTrk system.
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28
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36749040524
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GE Fanuc Embedded Systems, PCI to VME bus adapter (Model 618) 〈http://www.gefanucembedded.com〉.
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29
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36749033993
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Vertical Interface Board Documentation 〈http://www-linac.fnal.gov/LINAC/hardware/vmesys/boards/vi/viInfo.html〉.
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30
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36749015255
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Python Programming Language-Official Website 〈http://www.python.org〉.
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31
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36749004552
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TkInter Documentation Website 〈http://wiki.python.org/moin/TkInter〉.
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32
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36749103947
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W3C: Extensible Markup Language Website 〈http://www.w3.org/XML/〉.
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33
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36749025927
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The ADAPTIVE Communication Environment Website 〈http://www.cs.wustl.edu/∼schmidt/ACE.html〉.
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34
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36749086145
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R. Brun, et al., ROOT: An Object-Oriented Data Analysis Framework 〈http://root.cern.ch/root/〉.
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