High-speed, low-power correlated double sampling counter for column-parallel CMOS imagers

Electronics Letters

Volumn 43, Issue 24, 2007, Pages 1362-1364

  Lee, D ^a   Han, G ^a  

^a Yonsei University   (South Korea)

Author keywords

[No Author keywords available]

Indexed keywords

CIRCUIT SIMULATION; DIGITAL ARITHMETIC; ELECTRIC POWER UTILIZATION; IMAGE ANALYSIS; TRANSISTORS;

CORRELATED DOUBLE SAMPLING COUNTERS; PARALLEL CMOS IMAGERS; UP/DOWN COUNTERS;

CMOS INTEGRATED CIRCUITS;

EID: 36448940197     PISSN: 00135194     EISSN: None     Source Type: Journal    
DOI: 10.1049/el:20072490     Document Type: Article

References (5)

1. Carlson, B.S.: ' Comparison of modern CCD and CMOS image sensor technologies and systems for low resolution imaging ', Proc. Conf. on Sensors, June, 2002, 1, p. 171-176
2. Kawai, N., and Kawahito, S.: ' Noise analysis of high-gain, low-noise column readout circuits for CMOS image sensor ', IEEE Trans. Electron Devices, 2004, 51, p. 185-193 10.1109/TED.2003.822224 0018-9383
3. Yang, W., Kwon, O., Lee, J., Hwang, G., and Lee, S.: ' An integrated 800×600 CMOS imaging system ', IEEE ISSCC Dig. Tech. Papers, 1999, p. 304-305
4. Yoshihara, S., Nitta, Y., Kikuchi, M., Koseki, K., Ito, Y., Inada, Y., Kuramochi, S., Wakabayashi, H., Okano, M., Kuriyama, H., Inutsuka, J., Tajima, A., Nakajima, T., Kudoh, Y., Koga, F., Kasagi, Y., Watanabe, S., and Nomoto, T.: ' A 1/1.8-inch 6.4 mpixel 60 frames/s CMOS image sensor with seamless mode change ', IEEE J. Solid-State Circuits, 2006, p. 2998-3006 0018-9200
5. Yuan, J.: ' Efficient CMOS counter circuits ', Electron. Lett.24, 1988, p. 1311-1313