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Volumn , Issue , 2006, Pages

Web memory hierarchy learning and research environment

Author keywords

[No Author keywords available]

Indexed keywords

COMPUTER ARCHITECTURE; CURRICULA; LEARNING SYSTEMS; STUDENTS; USER INTERFACES;

EID: 36448934444     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1145/1275620.1275629     Document Type: Conference Paper
Times cited : (2)

References (21)
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    • MSCSim Home Page, http://www.mscsim.com.
    • MSCSim
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    • 20344377056 scopus 로고    scopus 로고
    • A Survey of Simulators Used in Computer Organization/Architecture Courses
    • Society for Computer Simulation SCS
    • Yurcik, W.; Wolffe, G. S.; Holliday, M. A; "A Survey of Simulators Used in Computer Organization/Architecture Courses", Summer Computer Simulation Conference (SCSC), Society for Computer Simulation (SCS), 2001.
    • (2001) Summer Computer Simulation Conference (SCSC)
    • Yurcik, W.1    Wolffe, G.S.2    Holliday, M.A.3
  • 7
    • 0032315076 scopus 로고    scopus 로고
    • Teaching Computer Architecture/Organisation using simulators
    • Grünbacher H., "Teaching Computer Architecture/Organisation using simulators", 28th Frontiers in Education Conference (FIE), pp. 1107-1112, 1998.
    • (1998) 28th Frontiers in Education Conference (FIE) , pp. 1107-1112
    • Grünbacher, H.1
  • 8
    • 0033729307 scopus 로고    scopus 로고
    • An Integrated Environment for Teaching Computer Architecture
    • Djordjevic, J.; Milenkovic, A.; Grbanovic. N.; "An Integrated Environment for Teaching Computer Architecture" IEEE Micro, Vol. 20, No. 3, pp. 66-74, 2000.
    • (2000) IEEE Micro , vol.20 , Issue.3 , pp. 66-74
    • Djordjevic, J.1    Milenkovic, A.2    Grbanovic, N.3
  • 9
    • 0036373552 scopus 로고    scopus 로고
    • Yurcik, W.; Wolffe, G. S.; Holliday, Mark A.; Osborne, Hugh. Teaching Computer Organization/Architecture With Limited, ACM SIGCSE Bulletin, 34, No. 1, pp. 176-180, 2002.
    • Yurcik, W.; Wolffe, G. S.; Holliday, Mark A.; Osborne, Hugh. "Teaching Computer Organization/Architecture With Limited", ACM SIGCSE Bulletin, Vol. 34, No. 1, pp. 176-180, 2002.
  • 11
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    • Cache Simulator Versão 1.9, 2003, Home Page http://www.ece.gatech. edu/research/labs/reveng/cachesim/index.html.
    • (2003) Cache Simulator Versão 1.9
  • 13
    • 36448990900 scopus 로고    scopus 로고
    • Shivakumar, P.; Jouppi, N. J.; Cacti 3.0, An Integrated Cache Timing, Power, and Area Model. Technical Report, Compaq Computer Corporation, 2001.
    • Shivakumar, P.; Jouppi, N. J.; Cacti 3.0, "An Integrated Cache Timing, Power, and Area Model". Technical Report, Compaq Computer Corporation, 2001.
  • 15
    • 36448995124 scopus 로고    scopus 로고
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    • Prima Cache Simulator, Home Page www.dsi.unimo.it/staff/st36/imagelab/ prima.html.
    • Prima Cache Simulator
  • 16
    • 0033728755 scopus 로고    scopus 로고
    • Simulation Model
    • R. N. Ibbett, HASE DLX Simulation Model. IEEE Micro, Vol. 20, No. 3, pp. 38-47, 2000.
    • (2000) IEEE Micro , vol.20 , Issue.3 , pp. 38-47
    • Ibbett, R.N.1    DLX, H.A.S.E.2
  • 19
    • 0020177251 scopus 로고
    • Cache memories
    • Smith, A. J.; "Cache memories", ACM Computing Surveys, Vol. 14, No. 3, pp. 473-530, 1982.
    • (1982) ACM Computing Surveys , vol.14 , Issue.3 , pp. 473-530
    • Smith, A.J.1


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.