Quilt packaging: High-density, high-speed interchip communications

IEEE Transactions on Advanced Packaging

Volumn 30, Issue 4, 2007, Pages 731-740

  Bernstein, Gary H ^a   Liu, Qing ^a   Yan, Minjun ^a   Sun, Zhuowen ^a   Kopp, David ^a   Porod, Wolfgang ^a   Snider, Greg ^a   Fay, Patrick ^a  

^a University of Notre Dame   (United States)

Author keywords

Bonding; chemical mechanical polishing (CMP); Chip scale packaging; Chip to chip interconnection; Copper plating; Deep reactive ion etching (DRIE); Multichip module (MCM); Packaging; Polishing machines; Superconnect; System on chip; System in package (SiP); System on chip (SoC); Wafer scale integration; Wafer scale integration (WSI)

Indexed keywords

CHEMICAL MECHANICAL POLISHING; COMPUTER SIMULATION; COPPER PLATING; FABRICATION; MULTICHIP MODULES; POLISHING MACHINES; WSI CIRCUITS;

CHIP-TO-CHIP INTERCONNECTION; DEEP REACTIVE ION ETCHING (DRIE); QUILT PACKAGING; SYSTEM ON CHIP; SYSTEM-IN-PACKAGE (SIP);

CHIP SCALE PACKAGES;

EID: 36349005942     PISSN: 15213323     EISSN: None     Source Type: Journal    
DOI: 10.1109/TADVP.2007.901643     Document Type: Article

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