Algorithm and Design of an Intelligent Digital Integrated Circuit for a Watermelon Harvesting Robot

Journal of Robotics and Mechatronics

Volumn 11, Issue 3, 1999, Pages 173-182

  Tokunaga, Yusuke ^a   Hakukawa, Toshihide ^b   Inoue, Takahiro ^a  

^a KUMAMOTO UNIVERSITY   (Japan)

^b Tcradync KK Kumamoto Facility   (Japan)

Author keywords

Coarsening; Edge Detection; FPGA; Noise filtering; Noise Reduction; Pattern Recognition

Indexed keywords

BINARY IMAGES; DIGITAL INTEGRATED CIRCUITS; EDGE DETECTION; FIELD PROGRAMMABLE GATE ARRAYS (FPGA); INTEGRATED CIRCUIT DESIGN; LOGIC SYNTHESIS; MACHINE DESIGN; TEMPLATE MATCHING; TIMING CIRCUITS;

CIRCULAR PATTERN; COARSENINGS; FIELD PROGRAMMABLE GATE ARRAY; FIELD PROGRAMMABLES; HARVESTING ROBOT; IMAGE-BASED; LOCATION PARAMETERS; MATCHING DEGREE; NOISE FILTERING; PROGRAMMABLE GATE ARRAY;

NOISE ABATEMENT;

EID: 36248945526     PISSN: 09153942     EISSN: 18838049     Source Type: Journal    
DOI: 10.20965/jrm.1999.p0173     Document Type: Article

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