SPER junction optimisation in 45nm CMOS devices

Extended Abstracts of the Fourth International Workshop on Junction Technology, IWJT 2004

Volumn 4, Issue , 2004, Pages 70-75

  Lindsay, R ^a   Severi, S ^a   Pawlak, B J ^b   Henson, K ^a   Lauwers, A ^a   Pages, X ^c   Satta, A ^a   Surdeanu, R ^b   Lendzian, H ^d   Maex, K ^a  

^a IMEC   (Belgium)

^b PHILIPS RESEARCH LABORATORIES   (Netherlands)

^c ASM BELGIUM   (Belgium)

^d VARIAN SEMICONDUCTOR EQUIPMENT ASSOCIATES   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

CHANNEL DEACTIVATION; CONTACT RESISTANCE; GATE LEAKAGE; SOLID PHASE EPITAXIAL REGROWTH (SPER);

ANNEALING; EPITAXIAL GROWTH; GATES (TRANSISTOR); OPTIMIZATION; POLYSILICON; SEMICONDUCTOR DOPING; THERMODYNAMIC STABILITY;

CMOS INTEGRATED CIRCUITS;

EID: 3543143623     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (9)

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7. A. Lauwers, et al, to be published in Mat. Res. Soc. Symp. C, 2004
8. S. Seven, et al, to be published in Mat. Res. Soc. Symp. C, 2004
9. S. Seven, et al, submitted to ULIS 2004.