Characterization of nano-grained high aspect ratio through-wafer copper interconnect column

Proceedings - Electronic Components and Technology Conference

Volumn , Issue , 2007, Pages 2011-2016

  Xu, Luhua ^a   Dixit, Pradeep ^a   Pang, John H L ^a   Miao, Jianmin ^a   Zhang, Xi ^b   Tu, King Ning ^b   Preisser, Robert ^c  

^a NANYANG TECHNOLOGICAL UNIVERSITY   (Singapore)

^b UNIVERSITY OF CALIFORNIA   (United States)

^c ATOTECH DEUTSCHLAND GMBH   (Germany)

Author keywords

[No Author keywords available]

Indexed keywords

MICROELECTRONIC DEVICES; NANO-SCALE GRAINS;

ASPECT RATIO; ELECTRIC CONDUCTIVITY; ELECTRODEPOSITION; ETCHING; GRAIN SIZE AND SHAPE; NANOSTRUCTURED MATERIALS; SILICON WAFERS;

ELECTRIC POWER SYSTEM INTERCONNECTION;

EID: 35348915635     PISSN: 05695503     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ECTC.2007.374078     Document Type: Conference Paper

References (13)

1. International Technology Roadmap for Semiconductors - Assembly and Packaging (2005 edition); http://public.itrs.net/Common/2005ITRS/Home2005.htm.
2. Alsarawi S.F., Abbott D. and P.D. Franzon, "A Review of 3-D Packaging Technology", IEEE Transactions on Components, Packaging and Manufacturing Technology - Part B, Vol. 21 (1998), pp. 2-14.
3. Takahashi K., Terao H., Tomita Y., Yamaji Y., Hoshino M., Sato T., Sunohara M., and Bonkohara M., "Current Status of Research and Development for Three-Dimensional Chip Stack Technology" Japanese Journal of Applied Physics, Vol. 40 (2001), pp. 3032-3037.
4. Seong J O., Kim C. and Baldwin D.F., "High Density, High Aspect Ratio Through-Wafer Electrical Interconnect Vias for MEMS Packaging", IEEE Transactions on Advanced Packaging, Vol. 26 (2003), pp. 302-309.
5. Dixit P., Miao J., and Preisser R., "Fabrication of high aspect ratio 35 μm pitch through-wafer copper interconnects by electroplating for 3-D wafer stacking", Electrochemical & Solid-State letters, Vol. 9, No. 10 (2006), pp. G305-G308.
6. Nguyen N.T., Boellaard E., Pham N.P., Kutchoukov V.G. and Sarro P.M., "Through-wafer copper electroplating for three-dimensional interconnects", Journal of Micromechanics and Microengineering, Vol. 12 (2002),pp. 395-399.
7. Sun J., Kondo K., Okamura T., Tomisaka M., Yonemura H., Hoshino M., and Takahashi K.," High-Aspect-Ratio Copper Via Filling Used for Three-Dimensional Chip Stacking", Journal of The Electrochemical Society, Vol. 150, (2003), pp. G355-G358.
8. Dixit P., and Miao J., "Aspect-ratio-dependent copper electrodeposition technique for high aspect-ratio through-hole plating", Journal of the Electrochemical Society, Vol. 153, No. 6 (2006), pp. G552-G559.
9. Lee S.W.R., Hon R., Zhang S.X.D., and Wong C.K., "3D stacked flip chip packaging with through silicon vias and copper plating or conductive adhesive filling", Proc. of 55th Electronic Components and Technology Conference, (2005) pp. 795-801.
10. Lei L., Shen Y., Chen X., Lihua Q., and Lu K., "Ultrahigh Strength and High Electrical Conductivity in Copper", Science, Vol. 304, (2004), pp. 422-426.
11. Shi X., Pang H.L.J., Zhang X.R., Liu Q. J., and Ying M., "In-Situ Micro-Digital Image Speckle Correlation Technique for Characterization of Material's Properties and Verification of Numerical Models", IEEE Transactions on Components and Packaging Technologies, Vol. 27, No. 4 (2004), pp. 659-667.
12. Xu L.H. and Pang H.L.J., "Nano-indentation characterization of Ni-Cu-Sn IMC layer subject to isothermal aging", Thin Solid Films, Vol. 504 (2006), pp. 362-366.
13. Xu L.H., Dixit P., Miao J. and Pang H.L.J.; Zhang X. Tu K.N. and Preisser R. Through-wafer electroplated copper interconnect with ultra-fine grains and high density of nano-twins, Applied Physics Letters, 90, 033111 2007