Low-temperature high-density chip-stack interconnection using compliant bump

Proceedings - Electronic Components and Technology Conference

Volumn , Issue , 2007, Pages 622-626

  Watanabe, Naoya ^a   Asano, Tanemasa ^b  

^a Kumamoto Technology and Industry Foundation   (Japan)

^b KYUSHU UNIVERSITY   (Japan)

Author keywords

[No Author keywords available]

Indexed keywords

ELECTRODES; INTERCONNECTION NETWORKS; PLASMA APPLICATIONS;

CHIP STACKING; PLASMA CLEANING; ROOM TEMPERATURE;

CHIP SCALE PACKAGES;

EID: 35348912501     PISSN: 05695503     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ECTC.2007.373861     Document Type: Conference Paper

References (11)

1. M. Koyanagi et al.: IEEE Micro 18 (1998) 17.
2. K. W. Guarini et al.: International Electron Devices Meeting Technical Digest (2002) pp. 943-945.
3. K. Kameyama et al.: Extended Abstracts of the 2004 International Conference on Solid State Devices and Materials (2004) pp. 276-277.
4. L. Schaper et al.: Extended Abstracts of the 2004 International Conference on Solid State Devices and Materials (2004) pp. 274-275.
5. K. Hara et al.: Proceedings of International Conference on Electronics Packaging (2005) pp. 161-166.
6. T. Fukushima et al.: International Electron Devices Meeting Technical Digest (2005) pp. 359-362.
7. A. W. Topol et al.: International Electron Devices Meeting Technical Digest (2005) pp. 363-366.
8. N. Watanabe, Y. Ootani and T. Asano: Jpn. J. Appl. Phys. 44 (2005) 2751.
9. N. Watanabe, T. Kojima and T. Asano: International Electron Devices Meeting Technical Digest (2005) pp. 687-690.
10. N. Watanabe and T. Asano: Proceedings of Electronic Components & Technology' Conference (2006) pp. 125-130.
11. N. Tanaka et al.: Proceedings of Electronic Components & Technology Conference (2006) pp. 814-818.