High density PoP (Package-on-Package) and package stacking development

Proceedings - Electronic Components and Technology Conference

Volumn , Issue , 2007, Pages 1397-1402

  Dreiza, Moody ^a   Yoshida, Akito ^a   Ishibashi, Kazuo ^b   Maeda, Tadashi ^c  

^a AMKOR TECHNOLOGY   (United States)

^b Nokia Japan   (Japan)

^c Panasonic Factory Solutions Co Ltd   (Japan)

Author keywords

[No Author keywords available]

Indexed keywords

CONSTRAINT THEORY; ELECTRONIC STRUCTURE; PRODUCT DESIGN; RELIABILITY ANALYSIS; SOLDERING ALLOYS;

DIE STACKING; PACKAGE-ON-PACKAGE (POP); PACKAGING CONFIGURATIONS; SOLDER ON PAD (SOP);

CHIP SCALE PACKAGES;

EID: 35348853106     PISSN: 05695503     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ECTC.2007.373977     Document Type: Conference Paper

References (6)

1. Yoshida, Akito et al., "A Study on Package Stacking Process for Package-on-Package (PoP)" ECTC, San Diego (2006)
2. Kada, Morihiro et al. "Advancements in Stacked Chip Scale Packaging (S-CSP), Provides System-in-a-Package Functionality for Wireless and Handheld Applications", Pan Pacific Microelectronics Symposium Conference, Maui, Hawaii, (2000)
3. Dreiza, Moody et al., "Stacked Package-on-Package Design Guidelines", International Wafer Level Packaging conference (2005)
4. JEDEC JC-11 committee Publication 95, Design Guide 4.22, Item: 11.02-726S
5. Maeda, Tadashi et al. "New concept paste material for improving PoP SMT yield in mobile products", KGD Packaging and Test Workshop (2006)
6. Dreiza, Moody et al., "Package on Package (PoP) Stacking and Board Level Reliability, Results of Joint Industry Study", IMAPS (2006)