The influence of interconnect line patterns using flat-surface and low-dielectric-loss material under high speed signal propagation

Proceedings - Electronic Components and Technology Conference

Volumn , Issue , 2007, Pages 1714-1719

  Sugimura, M ^a   Imai, H ^b   Nakayama, M ^c   Kawasaki, M ^a   Fujimura, M ^a   Oonuki, H ^c   Kawashima, O ^c   Morimoto, A ^b   Teramoto, A ^b   Sugawa, S ^b   Ohmi, T ^b  

^a ZEON CORPORATION   (Japan)

^b TOHOKU UNIVERSITY   (Japan)

^c Daisho Denshi Co Ltd   (Japan)

Author keywords

[No Author keywords available]

Indexed keywords

ELECTRIC POWER UTILIZATION; ELECTRONICS PACKAGING; MATHEMATICAL MODELS; MICROPROCESSOR CHIPS; PERMITTIVITY; SIGNAL PROCESSING; TIME DOMAIN ANALYSIS;

HIGH SPEED SIGNAL PROPAGATION; INTERCONNECT LINE PATTERNS; SEMICONDUCTOR PACKAGES; TIME DOMAIN REFLECTOMETRY (TDR); TIME DOMAIN TRANSMISSION (TDT);

DIELECTRIC MATERIALS;

EID: 35348846441     PISSN: 05695503     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ECTC.2007.374026     Document Type: Conference Paper

References (5)

1. International Technology Roadmap for Semiconductor (ITRSI 2006 Update. JEITA (Tokyo, 2006), [A book reference...]
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3. Wadell, B. C., Transmission line design handbook, ARTECH HOUSE, INC. (Norwood, MA, 1991), pp. 291-293. [A book reference...]
4. Sakurai, T. et al, "Simple formulas for two- and three-dimensional capacitances," IEEE Trans. Electron Devices, Vol. 30, No. 2 (1983), pp. 183-185. [A reference to a journal article...]
5. I. Morgan, S. P., "Effect of surface roughness on eddy current losses at microwave frequencies," J. Appl. Phys., Vol. 20, No. 4 (1949), pp. 352-362. [A reference to a journal article...]