메뉴 건너뛰기




Volumn 2778, Issue , 2003, Pages 1127-1130

A new reconfigurable-oriented method for canonical basis multiplication over a class of finite fields GF(2m)

Author keywords

[No Author keywords available]

Indexed keywords

SYSTOLIC ARRAYS;

EID: 35248860772     PISSN: 03029743     EISSN: 16113349     Source Type: Book Series    
DOI: 10.1007/978-3-540-45234-8_136     Document Type: Article
Times cited : (2)

References (9)
  • 1
    • 0004129394 scopus 로고
    • Menezes, A.J. (ed.): Kluwer Academic
    • Menezes, A.J. (ed.): Applications of Finite Fields. Kluwer Academic (1993)
    • (1993) Applications of Finite Fields
  • 3
    • 0034187223 scopus 로고    scopus 로고
    • Mastrovito Multiplier for General Irreducible Polynomials
    • Halbutogullari, A., Koç, Ç.K.: Mastrovito Multiplier for General Irreducible Polynomials. IEEE Trans. Computers, Vol.49, No.5 (2000) 503-518
    • (2000) IEEE Trans. Computers , vol.49 , Issue.5 , pp. 503-518
    • Halbutogullari, A.1    Koç, Ç.K.2
  • 5
    • 0032023646 scopus 로고    scopus 로고
    • Low-Complexity Bit-Parallel Canonical and Normal Basis Multipliers for a class of Finite Fields
    • Koç, Ç.K., Sunar, B.: Low-Complexity Bit-Parallel Canonical and Normal Basis Multipliers for a class of Finite Fields. IEEE Trans. Computers, Vol.47, No.3 (1998) 353-356
    • (1998) IEEE Trans. Computers , vol.47 , Issue.3 , pp. 353-356
    • Koç, Ç.K.1    Sunar, B.2
  • 6
    • 0035392553 scopus 로고    scopus 로고
    • Systematic Design of Original and Modified Mastrovito Multipliers for General Irreducible polynomials
    • Zhang, T., Parhi, K.K.: Systematic Design of Original and Modified Mastrovito Multipliers for General Irreducible polynomials. IEEE Trans. Computers, Vol.50, No.7 (2001) 734-749
    • (2001) IEEE Trans. Computers , vol.50 , Issue.7 , pp. 734-749
    • Zhang, T.1    Parhi, K.K.2
  • 8
    • 0036732285 scopus 로고    scopus 로고
    • m) with Reconfigurable Hardware
    • Kluwer Academic Publishers
    • m) with Reconfigurable Hardware. Acta Applicandae Mathematicae, Vol.73, No.3. Kluwer Academic Publishers (2002) 337-356
    • (2002) Acta Applicandae Mathematicae , vol.73 , Issue.3 , pp. 337-356
    • Imaña, J.L.1
  • 9
    • 0035518415 scopus 로고    scopus 로고
    • A Routability Driven Technology Mapping Algorithm for LUT Based FPGA Designs
    • Kao, C.C., Lai, Y.T.: A Routability Driven Technology Mapping Algorithm for LUT Based FPGA Designs. IEICE Trans. Fundamentals, Vol.E84-A, No.11 (2001) 2690-2696
    • (2001) IEICE Trans. Fundamentals , vol.E84-A , Issue.11 , pp. 2690-2696
    • Kao, C.C.1    Lai, Y.T.2


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.