FPGA implementation of multi-layer perceptrons for speech recognition

Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics)

Volumn 2778, Issue , 2003, Pages 1048-1052

  Ortigosa, E M ^a   Ortigosa, P M ^b   Canas A ^a   Ros, E ^a   Agis R ^a   Ortega, J ^a  

^a UNIVERSITY OF GRANADA   (Spain)

^b UNIVERSITY OF ALMERÍA   (Spain)

Author keywords

[No Author keywords available]

Indexed keywords

COMPUTATION THEORY; COMPUTER HARDWARE; EMBEDDED SYSTEMS; FIELD PROGRAMMABLE GATE ARRAYS (FPGA); HARDWARE; RECONFIGURABLE HARDWARE;

ABSTRACTION LEVEL; COMPUTATIONAL RESOURCES; FPGA IMPLEMENTATIONS; HARDWARE IMPLEMENTATIONS; MULTI LAYER PERCEPTRON; MULTI-LAYER PERCEPTRONS; REGISTER TRANSFER LEVEL; SILICON AREA;

SPEECH RECOGNITION;

EID: 35248823665     PISSN: 03029743     EISSN: 16113349     Source Type: Book Series    
DOI: 10.1007/978-3-540-45234-8_117     Document Type: Article

References (3)

1. Widrow, B., Lehr, M.: 30 years of adaptive neural networks: Perception, Madeline and Backpropagation. Proceedings of the IEEE, vol. 78, no. 9, pp.1415-1442 (1990)
2. Celoxica, http://www.celoxica.com/
3. Xilinx, http://www.xilinx.com/