Architectural synthesis of digital signal processing applications dedicated to submicron technologies

Proceedings of the IEEE International Conference on Electronics, Circuits, and Systems

Volumn 1, Issue , 2001, Pages 533-536

  Casseau, Emmanuel ^a   Jego, Christophe ^a   Martin, Eric ^a  

^a UNIVERSITÉ DE BRETAGNE SUD   (France)

Author keywords

[No Author keywords available]

Indexed keywords

ABSTRACTION LEVEL; ARCHITECTURAL SYNTHESIS; CIRCUIT INTERCONNECTIONS; DIGITAL SIGNALS; EFFICIENT DESIGNS; INTERCONNECTION COSTS; PATH CONSTRAINT; SUBMICRON TECHNOLOGIES; SYNTHESIS PROCESS;

CONCURRENT ENGINEERING; COST ACCOUNTING; JOB ANALYSIS; RAPID PROTOTYPING; SIGNAL PROCESSING; VLSI CIRCUITS;

COST BENEFIT ANALYSIS;

EID: 35148898949     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (11)

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