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Volumn 49, Issue 1, 2007, Pages 161-175

A tool for unbiased comparison between logarithmic and floating-point arithmetic

Author keywords

[No Author keywords available]

Indexed keywords

DIGITAL ARITHMETIC; DIGITAL LIBRARIES; FIELD PROGRAMMABLE GATE ARRAYS (FPGA); NUMBER THEORY;

EID: 35148852566     PISSN: 13875485     EISSN: None     Source Type: Journal    
DOI: 10.1007/s11265-007-0048-7     Document Type: Article
Times cited : (25)

References (27)
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    • Coleman, J.N.1    Chester, E.I.2
  • 6
    • 0034858753 scopus 로고    scopus 로고
    • Some Improvements on Multipartite Table Methods
    • N. Burgess and L. Ciminiera (Eds.), June Updated version of LIP research report 2000-38
    • F. de Dinechin and A. Tisserand, "Some Improvements on Multipartite Table Methods," in 15th IEEE Symposium on Computer Arithmetic, N. Burgess and L. Ciminiera (Eds.), June 2001, pp. 128-135. (Updated version of LIP research report 2000-38.)
    • (2001) 15th IEEE Symposium on Computer Arithmetic , pp. 128-135
    • De Dinechin, F.1    Tisserand, A.2
  • 7
    • 20244390636 scopus 로고    scopus 로고
    • Floating-point Sparse Matrix-vector Multiply for FPGAs
    • ACM Press
    • M. deLorimier and A. DeHon, "Floating-point Sparse Matrix-vector Multiply for FPGAs," in ACM/SIGDA Field-programmable Gate Arrays, ACM Press, 2005, pp. 75-85.
    • (2005) ACM/SIGDA Field-programmable Gate Arrays , pp. 75-85
    • Delorimier, M.1    Dehon, A.2
  • 11
    • 18644383778 scopus 로고    scopus 로고
    • FPGA-based Implementation of a Robust IEEE-754 Exponential Unit
    • IEEE
    • C. Doss and R. Riley, "FPGA-based Implementation of a Robust IEEE-754 Exponential Unit," in FPGAs for Custom Computing Machines, IEEE, 2004.
    • (2004) FPGAs for Custom Computing Machines
    • Doss, C.1    Riley, R.2
  • 17
    • 0026122066 scopus 로고
    • What Every Computer Scientist Should Know about Floating-point Arithmetic
    • 1
    • D. Goldberg, "What Every Computer Scientist Should Know about Floating-point Arithmetic," ACM Comput. Surv., vol. 23, no. 1, (Mar.) 1991, pp. 5-47.
    • (1991) ACM Comput. Surv. , vol.23 , pp. 5-47
    • Goldberg, D.1
  • 20
    • 14844338846 scopus 로고    scopus 로고
    • A Dual-path Logarithmic Number System Addition/Subtraction Scheme for FPGA
    • Sept. Lisbon
    • B. Lee and N. Burgess, "A Dual-path Logarithmic Number System Addition/Subtraction Scheme for FPGA," in Field-programmable Logic and Applications, (Sept.) 2003, Lisbon.
    • (2003) Field-programmable Logic and Applications
    • Lee, B.1    Burgess, N.2
  • 21
    • 0025516618 scopus 로고
    • An Architecture for Addition and Subtraction of Long Word Length Numbers in the Logarithmic Number System
    • Nov.
    • D. M. Lewis, "An Architecture for Addition and Subtraction of Long Word Length Numbers in the Logarithmic Number System," IEEE Trans. Comput., vol. 39, no. 11, (Nov.) 1990.
    • (1990) IEEE Trans. Comput. , vol.39 , Issue.11
    • Lewis, D.M.1
  • 22
    • 84950148723 scopus 로고    scopus 로고
    • Using Floating-point Arithmetic on FPGAs to Accelerate Scientific N-body Simulations
    • IEEE
    • G. Lienhart, A. Kugel, and R. Männer, "Using Floating-point Arithmetic on FPGAs to Accelerate Scientific N-body Simulations," in FPGAs for Custom Computing Machines, IEEE, 2002.
    • (2002) FPGAs for Custom Computing Machines
    • Lienhart, G.1    Kugel, A.2    Männer, R.3
  • 25
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    • A Novel Algorithm for Accurate Logarithmic Number System Subtraction
    • IEEE, (May)
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    • Paliouras, V.1    Stouraitis, T.2
  • 26
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  • 27
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    • Taylor, F.J.1    Gill, R.2    Joseph, J.3    Radke, J.4


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.