Dynamic power management for UML modeled applications on multiprocessor SoC

Proceedings of SPIE - The International Society for Optical Engineering

Volumn 6507, Issue , 2007, Pages

  Kukkala, Petri ^a   Arpinen, Tero ^b   Setälä, Mikko ^b   Hännikäinen, Marko ^b   Hämäläinen, Timo D ^b  

^a NOKIA RESEARCH CENTER   (United States)

^b TAMPERE UNIVERSITY OF TECHNOLOGY   (Finland)

Author keywords

Dynamic power management; FPGA; Multiprocessor SoC; UML 2.0; WLAN

Indexed keywords

COMPUTER HARDWARE; ELECTRIC POWER UTILIZATION; EMBEDDED SYSTEMS; FIELD PROGRAMMABLE GATE ARRAYS (FPGA); PROGRAM PROCESSORS; STATISTICS; SYSTEMS ANALYSIS;

CLOCK-GATING; DYNAMIC POWER MANAGEMENT; HARDWARE ACCELERATORS; MULTIPROCESSOR SOC;

UNIFIED MODELING LANGUAGE;

EID: 35148846274     PISSN: 0277786X     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1117/12.707328     Document Type: Conference Paper

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