In-chip overlay metrology for 45nm and 55nm processes

Proceedings of SPIE - The International Society for Optical Engineering

Volumn 6518, Issue PART 2, 2007, Pages

  Ku, Y S ^a   Tung, C H ^a   Li, Y P ^a   Pang, H L ^a   Ke, C M ^b   Wang, Y H ^b   Huang, D C ^b   Smith, N P ^c   Binns, L ^d  

^a INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTE   (Taiwan)

^b TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY   (Taiwan)

^c Nanometrics Incorporated   (Taiwan)

^d Nanometrics Inc   (United Kingdom)

Author keywords

Bar in bar; In chip; Optical metrology; Overlay; Overlay mark

Indexed keywords

DATA REDUCTION; IMAGING SYSTEMS; PROCESS CONTROL; PRODUCTION CONTROL; INTEGRATED CIRCUIT TESTING; NANOTECHNOLOGY; OPTICAL VARIABLES MEASUREMENT; SEMICONDUCTOR DEVICE MODELS; UNCERTAINTY ANALYSIS; WAFER BONDING;

IMAGE ASYMMETRY; OPTICAL IMAGING TOOLS; OPTICAL METROLOGY; OVERLAY MARKS;

MICROPROCESSOR CHIPS; CHIP SCALE PACKAGES;

EID: 35148827615     PISSN: 0277786X     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1117/12.713075     Document Type: Conference Paper

References (3)

1. Y Ku et al, "In-Chip overlay measurement by existing bright-field imaging optical tools", Proc SPIE 5752, 438-448 (2005)
2. Y Ku et al, "In-chip overlay metrology", Proc SPIE 6152 pp 615214-1 to 615314-12 (2006)
3. International Technology Roadmap for Semiconductors, ITRS, 2005 edition.