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Volumn 6520, Issue PART 1, 2007, Pages

Process window and interlayer aware OPC for the 32nm node

Author keywords

32nm node; Interlayer aware; OPC; Process window

Indexed keywords

IMAGE PROCESSING; LIGHTING; OPTICAL RESOLVING POWER; OPTICS; OPTIMIZATION; POLARIZATION;

EID: 35148817496     PISSN: 0277786X     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1117/12.714442     Document Type: Conference Paper
Times cited : (11)

References (3)
  • 2
    • 25144470584 scopus 로고    scopus 로고
    • Optimized Hardware and Software for Fast, Full Chip Simulation
    • Y. Cao, Y.W. Lu, L. Chen, and J. Ye, Optimized Hardware and Software for Fast, Full Chip Simulation, Proc. SPIE Vol. 5754, 2005
    • (2005) Proc. SPIE , vol.5754
    • Cao, Y.1    Lu, Y.W.2    Chen, L.3    Ye, J.4
  • 3
    • 35148817785 scopus 로고    scopus 로고
    • Predictive focus exposure matrix modeling for rull-chip lithography applications
    • L. Chen, Y. Cao, M. Preil, H. Liu, W. Shao, M. Feng, and J. Ye, Predictive focus exposure matrix modeling for rull-chip lithography applications, Proc. SPIE Vol. 6154, 2006
    • (2006) Proc. SPIE , vol.6154
    • Chen, L.1    Cao, Y.2    Preil, M.3    Liu, H.4    Shao, W.5    Feng, M.6    Ye, J.7


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.