An integrated performance model of disk arrays

Proceedings - IEEE Computer Society's Annual International Symposium on Modeling, Analysis, and Simulation of Computer and Telecommunications Systems, MASCOTS

Volumn 2003-January, Issue , 2003, Pages 296-305

  Varki, E ^a   Merchant, A ^b   Xu, J ^a   Qiu, X ^c  

^a UNIVERSITY OF NEW HAMPSHIRE   (United States)

^b HEWLETT PACKARD LABORATORIES   (United States)

^c FalconStor Software   (United States)

Author keywords

Adaptive arrays; Analytical models; Availability; Computational modeling; Computer science; Computer simulation; Performance analysis; Predictive models; Prefetching; Quality of service

Indexed keywords

ANALYTICAL MODELS; AVAILABILITY; COMPUTER SCIENCE; COMPUTER SIMULATION; QUALITY OF SERVICE;

ADAPTIVE ARRAYS; COMPUTATIONAL MODEL; PERFORMANCE ANALYSIS; PREDICTIVE MODELS; PREFETCHING;

QUALITY CONTROL;

EID: 35048904484     PISSN: 15267539     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/MASCOT.2003.1240674     Document Type: Conference Paper

References (32)

1. G. Alvarez, E. Borowsky, S. Go, T. H. Romer, R. Becker-Szendy, R. Golding, A. Merchant, M. Spasojevic, A. Veitch, and J. Wilkes. Minerva: An automated resource provisioning tool for large-scale storage systems. ACM Transactions on Computer Systems, 19(4):483-518, Nov. 2001.
2. E. Anderson, M. Hobbs, K. Keeton, S. Spence, M. Uysal, and A. Veitch. Hippodrome: running circles around storage administration. In Proceedings of the USENIX Conference on File and Storage Technologies (FAST), pages 175-88, Monterey, CA, Jan. 2002.
3. E. Bachmat and J. Schindler. Analysis of methods for scheduling low priority disk drive tasks. In Proc. ACM SIGMETRICS, pages 55-65, Marina del Ray, CA, June 2002.
4. S. Chen and D. Towsley. The design and evaluation of RAID 5 and parity striping disk array architectures. Journal of Parallel and Distributed Computing, 17(1-2):58-74, Jan. 1993.
5. S. Chen and D. Towsley. A performance evaluation of RAID architectures. IEEE Transactions on Computers, 45(10):1116-30, Oct. 1996.
6. R. Cooper. Introduction to Queueing Theory. Mercury Press/Fairchild Publications, MD, 1990.
7. W. V. Courtright II. A transactional approach to redundant disk array implementation. PhD thesis, Department Electrical Engineering and Computer Science, Carnegie-Mellon University, May 1997.
8. G. R. Ganger. System-oriented evaluation of I/O subsystem performance. Technical Report CSE-TR-243-95, University of Michigan, June 1995.
9. Hewlett-Packard Company. HP SureStore E Disk Array FC60 User's guide, Dec. 2000. Pub. No. A5277-90001.
10. N. L. Johnson, S. Kotz, and N. Balakrishnan. Continuous Univariate Distributions, Volume 2. Wiley, May 1995.
11. M. Kim and A. Tantawi. Asynchronous disk interleaving: approximating access delays. IEEE Transactions on Computers, 40(7):801-10, July 1991.
12. A. Kuratti and W. H. Sanders. Performance analysis of the RAID5 disk array. In Proceedings of the IEEE International Computer Performance and Dependability Symposium, pages 236-245, Erlangen, Germany, 24-26 1995.
13. E. Lazowska, J. Zahorjan, G. Graham, and K. Sevcik. Quantitative System Performance - Computer System Analysis Using Queueing Network Models. Prentice-Hall, New Jersey, 1984.
14. E. Lee and R. Katz. An analytic performance model of disk arrays. In Proc. ACM SIGMETRICS, pages 98-109, Santa Clara, CA, May 1993.
15. J. Menon. Performance of RAID 5 disk arrays with read and write caching. Distributed and Parallel Databases, 2(3):261-293, July 1994.
16. J. Menon and D. Mattson. Performance of disk arrays in transaction processing environments. In Proc. 12th ICDCS, pages 302-309, Yokohama, Japan, June 1992.
17. A. Merchant and P. Yu. Analytic modeling and comparisons of striping strategies for replicated disk arrays. IEEE Transactions on Computers, 44(3):419-33, Mar. 1995.
18. A. Merchant and P. Yu. Analytic modeling of clustered RAID with mapping based on nearly random permutation. IEEE Transactions on Computers, 45(3):367-73, Mar. 1996.
19. A. Merchant and P. S. Yu. An analytical model of reconstruction time in mirrored disks. Performance Evaluation, 20(1-3):115-29, May 1994.
20. S. Mishra and P. Mohapatra. Performance study of RAID5 disk arrays with data and parity cache. In Proc. of the International Conference on Parallel Processing, pages 74-85, Aug. 1996.
21. C. Ruemmler and J. Wilkes. Unix disk access patterns. In Proc. Winter USENIX, pages 405-420, San Diego, CA, Jan. 1993.
22. Seagate Corporation. Cheetah 73 Family: ST173404LW/LWV/LC/LCV Product Manual, Vol. 1. http://www.seagate.com/support/disc/manuals/scsi/83329478f.pdf.
23. E. Shriver, A. Merchant, and J. Wilkes. An analytic behavior model for disk drives with readahead caches and request reordering. In Proc. ACM SIGMETRICS, pages 182-91, Madison, WI, June 1998.
24. A. Thomasian and J. Menon. Performance analysis of RAID5 disk arrays with a vacationing server model for rebuild mode operation. In Proc. 10th Intl. Conf. Data Eng., pages 111-119, Houston, TX, Feb. 1994.
25. A. Thomasian and J. Menon. RAID5 performance with distributed sparing. IEEE Transactions on Parallel and Distributed Systems, 8(6):640-57, June 1997.
26. M. Uysal, G. Alvarez, and A. Merchant. A modular, analytical model for modern disk arrays. In IEEE MASCOTS, pages 183-193, Cincinnati, OH, Aug. 2001.
27. E. Varki. Mean value technique for closed fork-join networks. In Proc. ACM SIGMETRICS, pages 103-112, Atlanta, GA, May 1999.
28. E. Varki, A. Merchant, J. Xu, and X. Qiu. An integrated model of disk arrays under synchronous I/O workloads. Technical report, University of New Hampshire, Jan. 2003.
29. A. Varma and Q. Jacobson. Destage algorithms for disk arrays with nonvolatile caches. IEEE Transactions on Computers, 47(2):228-235, Feb. 1998.
30. J. Wilkes. The Pantheon storage-system simulator. Technical Report HPL-1999-127, Hewlett-Packard Laboratories, Dec. 1995.
31. T. M. Wong and J. Wilkes. My cache or yours? making storage more exclusive. In Proc. of the USENIX Annual Technical Conference, pages 161-175, Monterey, CA, June 2002.
32. W. S. Wong and R. J. T. Morris. Benchmark synthesis using the LRU cache hit function. IEEE Transactions on Computers, 37(6):637-645, June 1988.