Yield learning methodology in early technology development

ASMC (Advanced Semiconductor Manufacturing Conference) Proceedings

Volumn , Issue , 2007, Pages 333-340

  Ouyang, Xu ^a   Riggs, David ^a   Ahsan, Ishtiaq ^a   Patterson, Oliver D ^a   Lea, Dallas M ^a   Ebersman, Benjamin ^a   Hawkins, Katherine V ^a   Miller, Keith ^b   Fox, Stephen ^a   Rice, James ^a  

^a IBM   (United States)

^b ADVANCED MICRO DEVICES   (United States)

Author keywords

Critical length; Early technology development; Grand pareto; Parametric yield model; SRAM stability; Systematic yield model; TPLY; Voltage contrast; Yield model; Yield step up plan

Indexed keywords

PROCESS CONTROL; STATIC RANDOM ACCESS STORAGE; SYSTEM STABILITY;

CRITICAL LENGTH; EARLY TECHNOLOGY DEVELOPMENT; PARAMETRIC YIELD MODEL; SYSTEMATIC YIELD MODEL; VOLTAGE CONTRAST; YIELD MODEL; YIELD STEP UP PLAN;

SEMICONDUCTOR DEVICE MANUFACTURE;

EID: 34748920934     PISSN: 10788743     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ASMC.2007.375059     Document Type: Conference Paper

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