A VLSI architecture design of an edge based fast intra prediction mode decision algorithm for h.264/avc

Proceedings of the ACM Great Lakes Symposium on VLSI, GLSVLSI

Volumn , Issue , 2007, Pages 20-24

  Li, Shen ^a   Wei, Xianghui ^a   Ikenaga, Takeshi ^a   Goto, Satoshi ^a  

^a WASEDA UNIVERSITY   (Japan)

Author keywords

Fast intra prediction mode decision; H.264; VLSI architecture

Indexed keywords

ALGORITHMS; CMOS INTEGRATED CIRCUITS; COMPUTATION THEORY; DECISION THEORY; HIGH DEFINITION TELEVISION; LOGIC DESIGN;

FAST INTRA PREDICTION MODE DECISION; MODE DECISION (MD) PROCESS; VLSI ARCHITECTURE;

VLSI CIRCUITS;

EID: 34748900522     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1145/1228784.1228795     Document Type: Conference Paper

References (9)

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7. JVT Test Model Ad Hoc Group, Evaluation sheet for motion estimation, Draft version 4, Feb. 19,2003.
8. Huang, Y.W., Hsieh, B.Y., Chen, T.C. and Chen, L.G. Analysis, fast algorithm, and VLSI architecture design for H.264/AVC intra frame coder, IEEE Trans. Circuits Syst. Video Tech., 15, 3, (Mar. 2005), 378-401.
9. Huang, Y.W. et al., A 1.3TOPS H.264/AVC Single Chip Encoder for HDTV Applications, In Digest of Technical Papers of the IEEE International Solid-State Circuit Conference (ISSCC05) (Feb. 2005). 128-129.