Optimizing ALD WN process for 65nm node CMOS contact application

Proceedings of the IEEE 2007 International Interconnect Technology Conference - Digest of Technical Papers

Volumn , Issue , 2007, Pages 105-107

  Chen, Y C ^a   Hung, T Y ^a   Chang, Y L ^a   Shieh, K ^a   Hsu, C L ^a   Huang, C ^a   Yan, W H ^b   Ashtiani, K ^b   Pisharoty, D ^b   Lei, W ^b   Chang, S ^b   Huang, F ^b   Collins, J ^b   Tzou, S F ^a  

^a UNITED MICROELECTRONICS CORPORATION   (Taiwan)

^b NOVELLUS SYSTEMS INC   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

CMOS INTEGRATED CIRCUITS; CONFORMATIONS; PHYSICAL PROPERTIES; PHYSICAL VAPOR DEPOSITION;

ALD TUNGSTEN NITRIDE; DEVICE FABRICATION; PROCESS INTEGRATION;

TUNGSTEN COMPOUNDS;

EID: 34748856369     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/iitc.2007.382361     Document Type: Conference Paper

References (5)

1. K. Frohberg, et al., Micro, October/November 2005, 39
2. K. Ashtiani, et al., SEMICON Korea 2006
3. D.G. Park et al., 2004 Symposium on VLSI Technology Digest of Technical Papers, 186
4. S. H. Lim, et al., 2005 Symposium on VLSI Technology Digest of Technical Papers, 190
5. A. Topol, et al., 2006 Symposium on VLSI Technology Digest of Technical Papers, s14-5