Novel technique to identify systematic and random defects during 65 nm and 45nm process development for faster yield learning

ASMC (Advanced Semiconductor Manufacturing Conference) Proceedings

Volumn , Issue , 2007, Pages 54-57

  Yeh, J H ^a   Park, Allen ^b  

^a UNITED MICROELECTRONICS CORPORATION   (Taiwan)

^b KLA TENCOR CORPORATION   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

CHARACTERIZATION; CLASSIFICATION (OF INFORMATION); COST EFFECTIVENESS; DEFECTS; PROBABILITY; PROCESS ENGINEERING;

CAVE DEFECTS; PROCESS DEVELOPMENT; RANDOM SAMPLING; REPEATER ANALYSIS;

LEARNING SYSTEMS;

EID: 34748854212     PISSN: 10788743     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ASMC.2007.375080     Document Type: Conference Paper

References (1)

1. Monahan K and Trafas, B. Design and Process Limited Yield at the 65nm Node and Beyond. SPIE 2005.