Robust integration of an ULK SiOCH dielectric (k=2.3) for high performance 32nm node BEOL

Proceedings of the IEEE 2007 International Interconnect Technology Conference - Digest of Technical Papers

Volumn , Issue , 2007, Pages 175-177

  Aimadeddine, M ^a,b   Jousseaume, V ^c   Arnal, V ^a,b   Favennec, L ^a,b   Farcy, A ^a,b   Zenasni, A ^c   Assous, M ^c   Vilmay, M ^d   Jullian, S ^e   Maury, P ^c   Delaye, V ^c   Jourdan, N ^a,b   Vanypre, T ^e   Brun, P ^c   Imbert, G ^a,b   LeFriec, Y ^a,b   Mellier, M ^e   Chaabouni, H ^a,b   Chapelon, L L ^a,b   Hamioud, K ^e   Volpi, F ^f   Louis, D ^c   Passemard, G ^a,b   Torres, J ^a,b   more..

^a STMICROELECTRONICS   (France)

^b CEA LETI Minatec ^*  (France)

^c CEA LETI   (France)

^d FREESCALE SEMICONDUCTOR INC   (United States)

^e NXP SEMICONDUCTORS   (France)

^f UNIV GRENOBLE ALPES   (France)

Author keywords

[No Author keywords available]

Indexed keywords

CAPACITANCE; LEAKAGE CURRENTS; POROUS MATERIALS; ROBUST CONTROL; SEMICONDUCTING SILICON COMPOUNDS;

BARRIER INTEGRITY; INTERLINE LEAKAGE; INTERMEDIATE LEVELS;

DIELECTRIC MATERIALS;

EID: 34748828153     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/iitc.2007.382382     Document Type: Conference Paper

References (5)

1. Y.N. Su et al. IEDM 2005
2. A. Farcy et al. MAM 2007
3. V. Arnal et al. IITC 2006
4. N. Posseme et al. IITC 2006
5. R. Fox et al. IEDM 2005