Design of mixed gates for leakage reduction

Proceedings of the ACM Great Lakes Symposium on VLSI, GLSVLSI

Volumn , Issue , 2007, Pages 263-268

  Sill, Frank ^a   You, Jiaixi ^a   Timmermann, Dirk ^a  

^a UNIVERSITY OF ROSTOCK   (Germany)

Author keywords

Gate leakage; Leakage current; Mixed gates; Threshold voltage

Indexed keywords

CIRCUIT SIMULATION; CMOS INTEGRATED CIRCUITS; ENERGY DISSIPATION; GATE DIELECTRICS; LEAKAGE CURRENTS; THRESHOLD VOLTAGE;

CURRENT DISSIPATION; GATE LEAKAGE; MIXED GATES; TRANSISTOR TYPES;

LOGIC GATES;

EID: 34748817059     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1145/1228784.1228851     Document Type: Conference Paper

References (17)

1. Kim, N.S., et. al.: Leakage Current: Moore's Law Meets Static Power, IEEE Computer, p. 68, no. 12, 2003.
2. Anis, M., and Elmasry, M. in Multi-Threshold CMOS Digital Circuits, Kluwer Academic Publishers (2003).
3. Tsai, Y., et. al.: Characterization & modeling of run-time techniques for leakage reduction. Tr. VLSI Syst. vol. 12,2004.
4. nd DAC, San Diego, 2005.
5. Maken, P.: et. al.: A Voltage Reduction Technique for Digital Systems, ISSCC, 1990.
6. Sundararajan, V. and Parhi, K.: Low Power Synthesis of Dual Vth CMOS VLSI Circuits, ISPLPED, 1999.
7. ox Circuits, 22* ICCD, San Jose, USA, 2004.
8. th DAC, 1999.
9. Sakurai, T. and Newton, R.: Alpha-Power Law MOSFET Model and its Applications to CMOS Inverter Delay and Other Formulas, IEEE JSSC, 25 (2), Apr. 1990.
10. Hu, S., et. al.: Berkeleyshort channel IGFET model, Dpt. of EECS, University of California, Berkeley, 2005.
11. Mukhopadhyay, S. and Roy, K.: Modelling and Estimation of Total Leakage Current in Nanoscaled CMOS Devices Considering the Effect of Parameter Variation, ISLPED '03, Seoul, Korea, 2003.
12. Schuegraf, K. and Hu C. Hole injection SiO break down model for very low voltage life time extrapolation, IEEE Trans. Electron. Devices, vol.41, pp. 761-767, 1994.
13. Cao, Y., et. al.: New paradigm of predictive MOSFET and interconnect modeling for early circuit design, CICC, 2000.
14. No reference due to blind review
15. Bisdounis, L., et. al: Modeling the dynamic behavior of seriesconnected MOSFETs for delay analysis of multiple-input CMOS gates, ISCAS, USA, 1998.
16. Hansen, M., Yalcin, H., Hayes, J. P. Unveiling the ISCAS-85 Benchmarks: A Case Study in Reverse Engineering, IEEED&T, vol. 16, no. 3, pp. 72-80, July-Sept. 1999.
17. Lee, D., Kwong, W., Blaauw, D., and Sylvester, D. Analysis and minimization techniques for total leakage considering gate oxide leakage, 40"" DAC, Anaheim, USA, 2003