A 4320MIPS four-processor core SMP/AMP with individually managed clock frequency for low power consumption

Digest of Technical Papers - IEEE International Solid-State Circuits Conference

Volumn , Issue , 2007, Pages 100-102

  Yoshida, Yutaka ^a   Kamei, Tatsuya ^a   Hayase, Kiyoshi ^a   Shibahara, Shinichi ^a   Nishii, Osamu ^a   Hattori, Toshihiro ^a   Hasegawa, Atsushi ^a   Takada, Masashi ^b   Irie, Naohiko ^b   Uchiyama, Kunio ^b   Odaka, Toshihiko ^b   Takada, Kiwamu ^c   Kimura, Keiji ^d   Kasahara, Hironori ^d  

^a RENESAS TECHNOLOGY CORP   (Japan)

^b HITACHI LTD   (Japan)

^c Hitachi ULSI   (Japan)

^d WASEDA UNIVERSITY   (Japan)

Author keywords

[No Author keywords available]

Indexed keywords

CACHE MEMORY; CHIP SCALE PACKAGES; DIGITAL ARITHMETIC; ELECTRIC POWER UTILIZATION; PROGRAM PROCESSORS;

CLOCK STOP; DATA CACHE COHERENCY; PROCESSOR CORE;

MICROPROCESSOR CHIPS;

EID: 34548855675     PISSN: 01936530     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ISSCC.2007.373607     Document Type: Conference Paper

References (3)

1. K. Uchiyama, et al., "Embedded Processor Core with 64-Bit Architecture and Its System-On-Chip Integration for Digital Consumer," IEICE, pp. 139-149, Feb. 2001.
2. J. Shirako, et al., "Compiler Control Power Saving Scheme for Multi Core Processors," Proc. of The 18th International Workshop on Languages and Compilers for Parallel Computing (LCPC2005), Oct., 2005.
3. K. Kimura, Y. Wada, H. Nakano et al., "Multigrain Parallel Processing on Compiler Cooperative Multiprocessor," Workshop on Interaction Between Compilers and Computer Architectures, pp. 11-20, Feb., 2005.