A 40-to-800MHz locking multi-phase DLL

Digest of Technical Papers - IEEE International Solid-State Circuits Conference

Volumn , Issue , 2007, Pages

  Kim, Young Sang ^a   Park, Seung Jin ^a   Kim, Yong Sub ^b   Jang, Dong Bi ^b   Jeong, Seh Woong ^b   Park, Hong June ^a   Sim, Jae Yoon ^a  

^a Pohang University of Science and Technology (POSTECH)   (South Korea)

^b SAMSUNG Electronics   (South Korea)

Author keywords

[No Author keywords available]

Indexed keywords

CAPACITORS; CMOS INTEGRATED CIRCUITS; INTERPOLATION; PHASE LOCKED LOOPS; RESISTORS; SWITCHING;

DELAY MATRIX; DELAY STEP ERROR;

COMPUTER SOFTWARE;

EID: 34548855024     PISSN: 01936530     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ISSCC.2007.373416     Document Type: Conference Paper

References (5)

1. J. Pan et al., "A CMOS Multi-Format Read/Write SoC for 7× Blu-Ray/16× DVD/56× CD," ISSCC Dig. Tech. Papers, pp.572-573, 2005.
2. Y. Konno et al., "A CMOS 1×-16× Speed DVD Write Channel IC," IEEE J.Solid-State Circuits, pp.642-650, Mar., 2006.
3. I. Young, J. Greason and K. Wong, "A PLL Clock Generator with 5 to 110 MHz of Lock Range for Microprocessors," IEEE J.Solid-State Circuits, pp.1599-1607, Nov., 1992.
4. T. Lin and W. Kaiser, "A 900-MHz 2.5-mA CMOS Frequency Synthesizer with an Automatic SC Tuning Loop," IEEE J.Solid-State Circuits, pp.424-431, Mar., 2001
5. K. Kattmnann and J. Barrow, "A Technique for Reducing Differential Non-Linearity Errors in Flash A/D Converters," ISSCC Dig. Tech. Papers, pp.170-171, 1991.