An attachable wireless chip access interface for arbitrary data rate using pulse-based inductive-coupling through LSI package

Digest of Technical Papers - IEEE International Solid-State Circuits Conference

Volumn , Issue , 2007, Pages 360-608

  Ishikuro, Hiroki ^a   Sugahara, Toshihiko ^b   Kuroda, Tadahiro ^a  

^a KEIO UNIVERSITY   (Japan)

^b RENESAS TECHNOLOGY CORP   (Japan)

Author keywords

[No Author keywords available]

Indexed keywords

CMOS INTEGRATED CIRCUITS; MICROPROCESSOR CHIPS; TRANSCEIVERS; WIRELESS NETWORKS;

DATA RATE; INDUCTIVE-COUPLING; LOGIC-PROBING SYSTEM;

LSI CIRCUITS;

EID: 34548847971     PISSN: 01936530     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ISSCC.2007.373443     Document Type: Conference Paper

References (2)

1. N. Miura, et al., "A 195Gb/s 1.2W 3D-Stacked Inductive Inter-Chip Wireless Superconnect with Transmit Power Control Scheme," ISSCC Dig. Tech. Papers, pp. 264-265, Feb., 2005.
2. N. Miura, et al., "A 1Tb/s 3W Inductive-Coupling Transceiver for Inter-Chip Clock and Data Link," ISSCC Dig. Tech. Papers, pp. 424-425, Feb., 2006.