Optimization of the MuGFET performance on Super Critical-Strained SOI (SC-SSOI) substrates featuring raised source/drain and dual CESL

International Symposium on VLSI Technology, Systems, and Applications, Proceedings

Volumn , Issue , 2007, Pages

  Collaert, N ^a   Rooyackers, R ^a   Dilliway, G ^b   Iyengar, V ^c,d   Augendre, E ^a   Leys, F ^a   Cayrefourq, I ^e   Ghyselen, B ^e   Loo, R ^a   Jurczak, M ^a   Biesemans, S ^a  

^a IMEC   (Belgium)

^b UNIVERSITY OF SURREY   (United Kingdom)

^c UNIVERSITY OF LEUVEN   (Belgium)

^d University of North Carolina at Charlotte   (United States)

^e PARC TECHNOLOGIQUE DES FONTAINES   (France)

Author keywords

[No Author keywords available]

Indexed keywords

ELECTRIC CURRENTS; ELECTRON MOBILITY; OPTIMIZATION; SILICON ON INSULATOR TECHNOLOGY;

CONTACT ETCH STOP LAYERS (CESL); SHORT CHANNEL NMOS; SUPER CRITICAL STRAINED SSOI (SC-SSOI);

FIELD EFFECT TRANSISTORS;

EID: 34548844730     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/VTSA.2007.378972     Document Type: Conference Paper

References (5)

1. N. Collaert et al., VLSI Symp., p. 6465, 2006
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3. P. Verheyen et al., VLSI Symp., p. 194-195, 2005
4. S. Pidin et al., VLSI Symp., p. 54-55, 2004
5. A.V.-Y. Thean et al., VLSI Symp., p. 164-165, 2006