Low-power circuits for brain-machine interfaces

Proceedings - IEEE International Symposium on Circuits and Systems

Volumn , Issue , 2007, Pages 2068-2071

  Sarpeshkar, Rahul ^a   Wattanapanitch, Woradorn ^a   Rapoport, Benjamin I ^a   Arfin, Scott K ^a   Baker, Michael W ^a   Mandal, Soumyajit ^a   Fee, Michale S ^a   Musallam, Sam ^b   Andersen, Richard A ^b  

^a MASSACHUSETTS INSTITUTE OF TECHNOLOGY   (United States)

^b CALIFORNIA INSTITUTE OF TECHNOLOGY   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

ELECTRIC POWER SYSTEMS; INTERACTIVE COMPUTER SYSTEMS; LEARNING SYSTEMS; TELEMETERING; WIRELESS NETWORKS;

BRAIN-MACHINE INTERFACES; LOW-POWER CIRCUITS; MULTI-ELECTRODE ARRAYS; NEUROSCIENCE SYSTEMS; RADIO-FREQUENCY (RF) IMPEDANCE MODULATION;

USER INTERFACES;

EID: 34548839147     PISSN: 02714310     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/iscas.2007.378505     Document Type: Conference Paper

References (4)

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