LVDS serial AER link performance

Proceedings - IEEE International Symposium on Circuits and Systems

Volumn , Issue , 2007, Pages 1537-1540

  Miro Amarante L ^a   Jimenez Fernandez A ^a   Linares Barranco, A ^a   Gomez Rodriguez F ^a   Paz, R ^a   Jimenez G ^a   Civit, A ^a   Serrano Gotarredona, R ^b  

^a UNIVERSITY OF SEVILLE   (Spain)

^b Centro Informatico Cientifico de Andalucia   (Spain)

Author keywords

[No Author keywords available]

Indexed keywords

DATA TRANSFER; FIELD PROGRAMMABLE GATE ARRAYS (FPGA); HIERARCHICAL SYSTEMS; IMAGE PROCESSING; MICROPROCESSOR CHIPS; TRANSCEIVERS;

ADDRESS-EVENT-REPRESENTATION (AER); LVDS; PROCESSING SYSTEMS; SPEED DIGITAL PARALLEL BUS; VXSI CHIPS;

COMMUNICATION;

EID: 34548837786     PISSN: 02714310     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/iscas.2007.378704     Document Type: Conference Paper

References (10)

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