256-channel neural recording microsystem with On-Chip 3D electrodes

Digest of Technical Papers - IEEE International Solid-State Circuits Conference

Volumn , Issue , 2007, Pages 160-162

  Aziz, Joseph ^a   Genov, Roman ^a   Derchansky, Miron ^a,b   Bardakjlan, Berj ^a   Carlen, Peter ^a,b  

^a UNIVERSITY OF TORONTO   (Canada)

^b TORONTO WESTERN HOSPITAL   (Canada)

Author keywords

[No Author keywords available]

Indexed keywords

CHANNEL CAPACITY; INTERFACES (MATERIALS); MICROELECTRODES; MICROPROCESSOR CHIPS; NEURAL NETWORKS; SPURIOUS SIGNAL NOISE;

CIRCUIT DESIGN; COMPRESSION CIRCUITS; NEURAL RECORDING INTERFACES; SWITCHED CAPACITORS;

MICROSYSTEMS;

EID: 34548830781     PISSN: 01936530     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ISSCC.2007.373637     Document Type: Conference Paper

References (6)

1. R. Olsson, K. Wise, "A Three-Dimensional Neural Recording Microsystem with Implantable Data Compression Circuitry," ISSCC Dig. Tech. Papers, pp. 558-559, Feb., 2005.
2. R. Harrison, et al., "A Low-Power Integrated Circuit for a Wireless 100-Electrode Neural Recording System," ISSCC Dig. Tech. Papers, pp. 554-555, Feb., 2006.
3. S. O'Driscoll, et al., "Neurons to Silicon: Implantable Prosthesis Processor," ISSCC Dig. Tech. Papers, pp. 552-553, Feb., 2006.
4. F. Heer, et al., "CMOS Microelectrode Array for Bidirectional Interaction with Neuronal Networks," IEEE J. Solid-State Circuits, vol. 41, pp. 1620-1629, July, 2006.
5. R. Harrison, C. Charles, "A Low-Power Low-Noise CMOS Amplifier for Neural Recording Applications," IEEE J. Solid-State Circuits, vol. 38, pp. 958-965, June, 2003.
6. J. Aziz, et al., "256-Channel Integrated Neural Interface and Spatio-Temporal Signal Processor," IEEE Proc. ISCAS, pp. 5075-5078, May, 2006.