A 1-to-2GHz 4-phase on-chip clock generator with timing-margin test capability

Digest of Technical Papers - IEEE International Solid-State Circuits Conference

Volumn , Issue , 2007, Pages 174-176

  Kaeriyama, Shunichi ^a   Kajita, Mikihiro ^a   Mizuno, Masayuki ^a  

^a NEC CORPORATION   (Japan)

Author keywords

[No Author keywords available]

Indexed keywords

CMOS INTEGRATED CIRCUITS; ELECTRIC CLOCKS; JITTER; SPECTRAL RESOLUTION; TUNING;

CLOCK-PERIOD DITHERING TECHNIQUES; DISTURBANCE-CONTROL FUNCTIONS; FREQUENCY TUNING RESOLUTION; ON-CHIP CLOCK GENERATORS;

ELECTRIC GENERATORS;

EID: 34548828226     PISSN: 01936530     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ISSCC.2007.373350     Document Type: Conference Paper

References (4)

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2. K. Nose, A. Shibayama, H. Kodama, et al., "Deterministic Inter-Core Synchronization with Periodically All-in-Phase Clocking for Low-Power Multi-Core SoCs," ISSCC Dig. Tech. Papers, pp. 296-297, Feb., 2005.
3. S. Sidiropoulos and M. Horowitz, "A Semi-Digital DLL with Unlimited Phase Shift Capability and 0.08-400MHz Operating Range," ISSCC Dig. Tech. Papers, pp. 332-333, Feb., 1997.
4. S. Fischer, R. Senthinathan, H. Rangchi and H. Yazdanmehr, "A 600MHz IA-32 Microprocessor with Enhanced Data Streaming for Graphics and Video," ISSCC Dig. Tech. Papers, pp. 98-99, Feb., 1999.