Hardware architecture of a parallel pattern matching engine

Proceedings - IEEE International Symposium on Circuits and Systems

Volumn , Issue , 2007, Pages 1369-1372

  Yadav, Meeta ^a   Venkatachaliah, Ashwini ^a   Franzon, Paul D ^a  

^a North Carolina State University   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

ALGORITHMS; COMPUTER HARDWARE; NETWORK SECURITY; PACKET NETWORKS; PATTERN MATCHING; QUALITY OF SERVICE;

HARDWARE ALGORITHMS; HARDWARE ARCHITECTURE; MULTIPLE CHARACTER MATCHING; PARALLEL PATTERN MATCHING ENGINES;

COMPUTER ARCHITECTURE;

EID: 34548827752     PISSN: 02714310     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/iscas.2007.378482     Document Type: Conference Paper

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