A study of design efficiency with a high-level language for FPGAs

Proceedings - 21st International Parallel and Distributed Processing Symposium, IPDPS 2007; Abstracts and CD-ROM

Volumn , Issue , 2007, Pages

  Zain ul Abdin, ^a   Svensson, Bertil ^a  

^a HALMSTAD UNIVERSITY   (Sweden)

Author keywords

[No Author keywords available]

Indexed keywords

COMPUTER HARDWARE; COMPUTER HARDWARE DESCRIPTION LANGUAGES; HIGH LEVEL LANGUAGES; MAINTAINABILITY; PRODUCTIVITY;

GATE-LEVEL GLUE LOGIC; MOBIUS LANGUAGE; PARALLEL PROCESSING LANGUAGE;

FIELD PROGRAMMABLE GATE ARRAYS (FPGA);

EID: 34548787179     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/IPDPS.2007.370394     Document Type: Conference Paper

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