Performance, cost, and energy evaluation of fat H-tree: A cost-efficient tree-based on-chip network

Proceedings - 21st International Parallel and Distributed Processing Symposium, IPDPS 2007; Abstracts and CD-ROM

Volumn , Issue , 2007, Pages

  Matsutani, Hiroki ^a   Koibuchi, Michihiro ^b   Amano, Hideharu ^a  

^a KEIO UNIVERSITY   (Japan)

^b NATIONAL INSTITUTE OF INFORMATICS   (Japan)

Author keywords

[No Author keywords available]

Indexed keywords

ELECTRIC POWER UTILIZATION; INTERCONNECTION NETWORKS; MICROPROCESSOR CHIPS; NETWORK MANAGEMENT; ROUTERS; ROUTING ALGORITHMS;

MICROARCHITECTURE DOMAINS; POWER ANALYSIS; TREE BASED NETWORKS;

TREES (MATHEMATICS);

EID: 34548760138     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/IPDPS.2007.370271     Document Type: Conference Paper

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