Cache-analyzer: Design space evaluation of configurable-caches in a single-pass

Proceedings of the International Workshop on Rapid System Prototyping

Volumn , Issue , 2007, Pages 3-9

  Silva, Andre ^a   Esmeraldo, Guilherme ^a   Barros, Edna ^a   Viana, Pablo ^b  

^a FEDERAL UNIVERSITY OF PERNAMBUCO   (Brazil)

^b FEDERAL UNIVERSITY OF ALAGOAS   (Brazil)

Author keywords

[No Author keywords available]

Indexed keywords

COMPUTER SIMULATION; ENERGY UTILIZATION; MATHEMATICAL MODELS; SYSTEMS ANALYSIS; TUNING;

MEMORY CACHE TUNING; MEMORY HIERARCHY;

CACHE MEMORY;

EID: 34548758509     PISSN: 10746005     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/RSP.2007.15     Document Type: Conference Paper

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