-
1
-
-
0035391629
-
A new contactless smart card IC using an on-chip antenna and an asynchronous microcontroller
-
A. Abrial, J. Bouvier, M. Renaudin, P. Senn, and P. Vivet, "A new contactless smart card IC using an on-chip antenna and an asynchronous microcontroller," IEEE Journal of Solid-State Circuits, vol. 36, no. 7, pp. 1101-1107, 2001.
-
(2001)
IEEE Journal of Solid-State Circuits
, vol.36
, Issue.7
, pp. 1101-1107
-
-
Abrial, A.1
Bouvier, J.2
Renaudin, M.3
Senn, P.4
Vivet, P.5
-
3
-
-
18144420677
-
Statistical timing analysis using bounds
-
A. Agarwal, D. Blaauw, V. Zolotov, and S. Vrudhula, "Statistical timing analysis using bounds," in Design, Automation and Test in Europe (DATE), pp. 10062-10067, 2003.
-
(2003)
Design, Automation and Test in Europe (DATE)
, pp. 10062-10067
-
-
Agarwal, A.1
Blaauw, D.2
Zolotov, V.3
Vrudhula, S.4
-
5
-
-
0036045933
-
HW/SW partitioning and code generation of embedded control applications on a reconfigurable architecture platform
-
Estes Park, Colorado, USA, May 6-8
-
M. Baleani, F. Gennari, Y. Jiang, Y. Patel, R. K. Brayton, and A. L. Sangiovanni-Vincentelli, "HW/SW partitioning and code generation of embedded control applications on a reconfigurable architecture platform," in Proceedings of the Tenth International Symposium on Hardware/Software Codesign, CODES 2002, pp. 151-156, Estes Park, Colorado, USA, May 6-8 2002.
-
(2002)
Proceedings of the Tenth International Symposium on Hardware/Software Codesign, CODES 2002
, pp. 151-156
-
-
Baleani, M.1
Gennari, F.2
Jiang, Y.3
Patel, Y.4
Brayton, R.K.5
Sangiovanni-Vincentelli, A.L.6
-
6
-
-
0003557110
-
-
PhD thesis, Department of Computer Science, University of Manchester
-
A. Bardsley, Implementing Balsa Handshake Circuits. PhD thesis, Department of Computer Science, University of Manchester, 2000.
-
(2000)
Implementing Balsa Handshake Circuits
-
-
Bardsley, A.1
-
7
-
-
27944481008
-
Bridging the gap between asynchronous design and designers (Tutorial)
-
Mumbai
-
P. Beerel, J. Cortadella, and A. Kondratyev, "Bridging the gap between asynchronous design and designers (Tutorial)," in VLSI Design Conference, (Mumbai), 2004.
-
(2004)
VLSI Design Conference
-
-
Beerel, P.1
Cortadella, J.2
Kondratyev, A.3
-
8
-
-
33749596550
-
Slack matching asynchronous designs
-
March
-
P. A. Beerel, M. Davies, A. Lines, and N.-H. Kim, "Slack matching asynchronous designs," in Proc. International Symposium on Advanced Research in Asynchronous Circuits and Systems, pp. 184-194, March 2006.
-
(2006)
Proc. International Symposium on Advanced Research in Asynchronous Circuits and Systems
, pp. 184-194
-
-
Beerel, P.A.1
Davies, M.2
Lines, A.3
Kim, N.-H.4
-
9
-
-
2442546302
-
Telescopic units: Increasing the average throughput of pipelined designs by adaptive latency control
-
L. Benini, E. Macii, and M. Poncino, "Telescopic units: Increasing the average throughput of pipelined designs by adaptive latency control," in Proc. ACM/IEEE Design Automation Conference, pp. 22-27, 1997.
-
(1997)
Proc. ACM/IEEE Design Automation Conference
, pp. 22-27
-
-
Benini, L.1
Macii, E.2
Poncino, M.3
-
10
-
-
34548727556
-
Handel-C Language Reference Manual
-
Celoxica, Handel-C Language Reference Manual. Celoxica. 2003.
-
(2003)
Celoxica
-
-
Celoxica1
-
12
-
-
0036054368
-
Resynthesis and peephole transformations for the optimization of large-scale asynchronous systems
-
June
-
T. Chelcea and S. M. Nowick, "Resynthesis and peephole transformations for the optimization of large-scale asynchronous systems," in Proc. ACM/IEEE Design Automation Conference, June 2002.
-
(2002)
Proc. ACM/IEEE Design Automation Conference
-
-
Chelcea, T.1
Nowick, S.M.2
-
14
-
-
0022325609
-
A design methodology for concurrent VLSI systems
-
IEEE Computer Society Press
-
T.-A. Chu, C. K. C. Leung, and T. S. Wanuga, "A design methodology for concurrent VLSI systems," in Proc. International Conf. Computer Design (ICCD), pp. 407-410, IEEE Computer Society Press, 1985.
-
(1985)
Proc. International Conf. Computer Design (ICCD)
, pp. 407-410
-
-
Chu, T.-A.1
Leung, C.K.C.2
Wanuga, T.S.3
-
15
-
-
77957932361
-
FLEETzero: An asynchronous switch fabric chip experiment
-
IEEE Computer Society Press, March
-
W. S. Coates, J. K. Lexau, I. W. Jones, S. M. Fairbanks, and I. E. Sutherland, "FLEETzero: An asynchronous switch fabric chip experiment," in Proc. International Symposium on Advanced Research in Asynchronous Circuits and Systems, pp. 173-182, IEEE Computer Society Press, March 2001.
-
(2001)
Proc. International Symposium on Advanced Research in Asynchronous Circuits and Systems
, pp. 173-182
-
-
Coates, W.S.1
Lexau, J.K.2
Jones, I.W.3
Fairbanks, S.M.4
Sutherland, I.E.5
-
16
-
-
0000549481
-
Marked directed graphs
-
F. Commoner, A. W. Holt, S. Even, and A. Pnueli, "Marked directed graphs," Journal of Computer and System Sciences, vol. 5, pp. 511-523, 1971.
-
(1971)
Journal of Computer and System Sciences
, vol.5
, pp. 511-523
-
-
Commoner, F.1
Holt, A.W.2
Even, S.3
Pnueli, A.4
-
17
-
-
0031096959
-
Petrify: A tool for manipulating concurrent specifications and synthesis of asynchronous controllers
-
March
-
J. Cortadella, M. Kishinevsky, A. Kondratyev, L. Lavagno, and A. Yakovlev, "Petrify: A tool for manipulating concurrent specifications and synthesis of asynchronous controllers," IEICE Transactions on Information and Systems, vol. E80-D, no. 3, pp. 315-325, March 1997.
-
(1997)
IEICE Transactions on Information and Systems
, vol.E80-D
, Issue.3
, pp. 315-325
-
-
Cortadella, J.1
Kishinevsky, M.2
Kondratyev, A.3
Lavagno, L.4
Yakovlev, A.5
-
18
-
-
0043222261
-
-
Springer-Verlag
-
J. Cortadella, M. Kishinevsky, A. Kondratyev, L. Lavagno, and A. Yakovlev, Logic Synthesis of Asynchronous Controllers and Interfaces. Springer-Verlag, 2002.
-
(2002)
Logic Synthesis of Asynchronous Controllers and Interfaces
-
-
Cortadella, J.1
Kishinevsky, M.2
Kondratyev, A.3
Lavagno, L.4
Yakovlev, A.5
-
19
-
-
3042565270
-
From synchronous to asynchronous: An automatic approach
-
February
-
J. Cortadella, A. Kondratyev, L. Lavagno, K. Lwin, and C. Sotiriou, "From synchronous to asynchronous: An automatic approach," in Proc. Design, Automation and Test in Europe (DATE), pp. 1368-1369, February 2004.
-
(2004)
Proc. Design, Automation and Test in Europe (DATE)
, pp. 1368-1369
-
-
Cortadella, J.1
Kondratyev, A.2
Lavagno, L.3
Lwin, K.4
Sotiriou, C.5
-
20
-
-
33748316690
-
Desynchronization: Synthesis of asynchronous circuits from synchronous specifications
-
October
-
J. Cortadella, A. Kondratyev, L. Lavagno, and C. Sotiriou, "Desynchronization: Synthesis of asynchronous circuits from synchronous specifications," IEEE Transactions on Computer-Aided Design, vol. 25, no. 10, pp. 1904-1921, October 2006.
-
(2006)
IEEE Transactions on Computer-Aided Design
, vol.25
, Issue.10
, pp. 1904-1921
-
-
Cortadella, J.1
Kondratyev, A.2
Lavagno, L.3
Sotiriou, C.4
-
21
-
-
34548798239
-
Haste language reference manual
-
Tech. Rep
-
M. de Wit and A. Peeters, "Haste language reference manual," Tech. Rep., 2006.
-
(2006)
-
-
de Wit, M.1
Peeters, A.2
-
23
-
-
0036173333
-
Balsa: An asynchronous hardware synthesis language
-
D. Edwards and A. Bardsley, "Balsa: An asynchronous hardware synthesis language," The Computer Journal, vol. 45, no. 1, pp. 12-18, 2002.
-
(2002)
The Computer Journal
, vol.45
, Issue.1
, pp. 12-18
-
-
Edwards, D.1
Bardsley, A.2
-
25
-
-
15044339297
-
Razor: Circuit-level correction of timing errors for low-power operation
-
November
-
D. Ernst, S. Das, S. Lee, D. Blaauw, T. Austin, T. Mudge, N. S. Kim, and K. Flautner, "Razor: Circuit-level correction of timing errors for low-power operation," IEEE Micro, November 2004.
-
(2004)
IEEE Micro
-
-
Ernst, D.1
Das, S.2
Lee, S.3
Blaauw, D.4
Austin, T.5
Mudge, T.6
Kim, N.S.7
Flautner, K.8
-
26
-
-
34548804570
-
Logically Determined Design: Clockless System Design with NULL Convention Logic
-
K. M. Fant, Logically Determined Design: Clockless System Design with NULL Convention Logic. John Wiley Sz Sons, 2005.
-
(2005)
John Wiley Sz Sons
-
-
Fant, K.M.1
-
27
-
-
0029727739
-
NULL conventional logic: A complete and consistent logic for asynchronous digital circuit synthesis
-
K. M. Fant and S. A. Brandt, "NULL conventional logic: A complete and consistent logic for asynchronous digital circuit synthesis," in International Conference on Application-specific Systems, Architectures, and Processors, pp. 261-273, 1996.
-
(1996)
International Conference on Application-specific Systems, Architectures, and Processors
, pp. 261-273
-
-
Fant, K.M.1
Brandt, S.A.2
-
29
-
-
2942670415
-
High performance asynchronous ASIC back-end design flow using single-track full-buffer standard cells
-
IEEE Computer Society Press, April
-
M. Ferretti, R., Ozdag, and P. Beerel, "High performance asynchronous ASIC back-end design flow using single-track full-buffer standard cells," in Proc. International Symposium on Advanced Research in Asynchronous Circuits and Systems, pp. 95-105, IEEE Computer Society Press, April 2004.
-
(2004)
Proc. International Symposium on Advanced Research in Asynchronous Circuits and Systems
, pp. 95-105
-
-
Ferretti, M.1
Ozdag, R.2
Beerel, P.3
-
33
-
-
0003885785
-
Minimalist: An environment for the synthesis, verification and testability of burst-mode asynchronous machines
-
CUCS-020-99, Columbia University, NY, July
-
R. M. Fuhrer, S. M. Nowick, M. Theobald, N. K. Jha, B. Lin, and L. Plana, "Minimalist: An environment for the synthesis, verification and testability of burst-mode asynchronous machines," Tech. Rep. TR CUCS-020-99, Columbia University, NY, July 1999.
-
(1999)
Tech. Rep. TR
-
-
Fuhrer, R.M.1
Nowick, S.M.2
Theobald, M.3
Jha, N.K.4
Lin, B.5
Plana, L.6
-
35
-
-
0030173207
-
Four-phase micropipeline latch control circuits
-
June
-
S. B. Furber and P. Day, "Four-phase micropipeline latch control circuits," IEEE Transactions on VLSI Systems, vol. 4, no. 2, pp. 247-253, June 1996.
-
(1996)
IEEE Transactions on VLSI Systems
, vol.4
, Issue.2
, pp. 247-253
-
-
Furber, S.B.1
Day, P.2
-
36
-
-
77957944088
-
AMULET3i -an asynchronous system-on-chip
-
IEEE Computer Society Press, April
-
J. D. Garside, W. J. Bainbridge, A. Bardsley, D. A. Edwards, S. B. Furber, J. Liu, D. W. Lloyd, S. Mohammadi, J. S. Pepper, O. Petlin, S. Temple, and J. V. Woods, "AMULET3i -an asynchronous system-on-chip," in Proc. International Symposium on Advanced Research in Asynchronous Circuits and Systems, pp. 162-175, IEEE Computer Society Press, April 2000.
-
(2000)
Proc. International Symposium on Advanced Research in Asynchronous Circuits and Systems
, pp. 162-175
-
-
Garside, J.D.1
Bainbridge, W.J.2
Bardsley, A.3
Edwards, D.A.4
Furber, S.B.5
Liu, J.6
Lloyd, D.W.7
Mohammadi, S.8
Pepper, J.S.9
Petlin, O.10
Temple, S.11
Woods, J.V.12
-
37
-
-
34548706682
-
Simple designs aren't easy, speaker says
-
R. Goering, "Simple designs aren't easy, speaker says," EE Times, http:// www.eetimes.com/showArticle.jhtml?articleID=184400784, no. 03/28/2006, 2006.
-
(2006)
EE Times
, Issue.3-28
-
-
Goering, R.1
-
42
-
-
2342548663
-
Information leakage attacks against smart card implementations of cryptographic algorithms and countermeasures -a survey
-
E. Hess, N. Janssen, B. Meyer, and T. Schutze, "Information leakage attacks against smart card implementations of cryptographic algorithms and countermeasures -a survey," in EUROSMART Security Conference, 2000.
-
(2000)
EUROSMART Security Conference
-
-
Hess, E.1
Janssen, N.2
Meyer, B.3
Schutze, T.4
-
43
-
-
0018005391
-
Communicating sequential processes
-
August
-
C. A. R. Hoare, "Communicating sequential processes," Communications of the ACM, vol. 21, no. 8, pp. 666-677, August 1978.
-
(1978)
Communications of the ACM
, vol.21
, Issue.8
, pp. 666-677
-
-
Hoare, C.A.R.1
-
45
-
-
29244432229
-
A 3.84 gbits/s AES crypto coprocessor with modes of operation in a, 0.18-um CMOS technology
-
Chicago, Illinois, USA, pp
-
A. Hodjat, D. D. Hwang, B. Lai, K. Tiri, and I. Verbauwhede, "A 3.84 gbits/s AES crypto coprocessor with modes of operation in a, 0.18-um CMOS technology," in 15th ACM Great Lakes symposium on VLSI, (Chicago, Illinois, USA), pp. 60-63, 2005.
-
(2005)
15th ACM Great Lakes symposium on VLSI
, pp. 60-63
-
-
Hodjat, A.1
Hwang, D.D.2
Lai, B.3
Tiri, K.4
Verbauwhede, I.5
-
46
-
-
0036287089
-
The optimal depth per pipeline stage is 6 to 8 fo4 inverter delays
-
IEEE CS Press
-
M. S. Hrishikesh, N. P. Jouppi, K. I. Farkas, D. Burger, S. W. Keckler, and P. Shivakumar, "The optimal depth per pipeline stage is 6 to 8 fo4 inverter delays," in 29th Int'l Symp. Computer Architecture., pp. 14-24, IEEE CS Press, 2002.
-
(2002)
29th Int'l Symp. Computer Architecture
, pp. 14-24
-
-
Hrishikesh, M.S.1
Jouppi, N.P.2
Farkas, K.I.3
Burger, D.4
Keckler, S.W.5
Shivakumar, P.6
-
47
-
-
0029404469
-
Testing asynchronous circuits: A survey
-
November
-
H. Hulgaard, S. M. Burns, and G. Borriello, "Testing asynchronous circuits: A survey," Integration, the VLSI Journal, vol. 19, no. 3, pp. 111-131, November 1995.
-
(1995)
Integration, the VLSI Journal
, vol.19
, Issue.3
, pp. 111-131
-
-
Hulgaard, H.1
Burns, S.M.2
Borriello, G.3
-
50
-
-
28144431710
-
A flexible 8b asynchronous microprocessor based on low-temperature poly-silicon TFT technology
-
February
-
N. Karaki, T. Nanmoto, H. Ebihara, S. Utsunomiya, S. Inoue, and T. Shimoda, "A flexible 8b asynchronous microprocessor based on low-temperature poly-silicon TFT technology," in International Solid State Circuits Conference., pp. 272-274, February 2005.
-
(2005)
International Solid State Circuits Conference
, pp. 272-274
-
-
Karaki, N.1
Nanmoto, T.2
Ebihara, H.3
Utsunomiya, S.4
Inoue, S.5
Shimoda, T.6
-
51
-
-
0033079595
-
-
C. H. (Kees) van Berkel, M. B. Josephs, and S. M. Nowick, Scanning the technology: Applications of asynchronous circuits, Proceedings of the IEEE, 87, no. 2, pp. 223-233, February 1999.
-
C. H. (Kees) van Berkel, M. B. Josephs, and S. M. Nowick, "Scanning the technology: Applications of asynchronous circuits," Proceedings of the IEEE, vol. 87, no. 2, pp. 223-233, February 1999.
-
-
-
-
52
-
-
77954509638
-
SNAP: A sensor-network asynchronous processor
-
IEEE Computer Society Press, May
-
C. Kelly, V. Ekanayake, and R. Manohar, "SNAP: A sensor-network asynchronous processor," in Proc. International Symposium on Advanced Research in Asynchronous Circuits and Systems, pp. 24-33, IEEE Computer Society Press, May 2003.
-
(2003)
Proc. International Symposium on Advanced Research in Asynchronous Circuits and Systems
, pp. 24-33
-
-
Kelly, C.1
Ekanayake, V.2
Manohar, R.3
-
54
-
-
0042774005
-
Designing an asynchronous bus interface
-
IEEE Computer Society Press, March
-
J. Kessels, A. Peeters, T. Kramer, M. Feuser, and K. Ully, "Designing an asynchronous bus interface," in Proc. International Symposium on Advanced Research in Asynchronous Circuits and Systems, pp. 108-117, IEEE Computer Society Press, March 2001.
-
(2001)
Proc. International Symposium on Advanced Research in Asynchronous Circuits and Systems
, pp. 108-117
-
-
Kessels, J.1
Peeters, A.2
Kramer, T.3
Feuser, M.4
Ully, K.5
-
57
-
-
0036646467
-
Design of asynchronous circuits using synchronous CAD tools
-
A. Kondratyev and K. Lwin, "Design of asynchronous circuits using synchronous CAD tools," IEEE Design & Test of Computers, vol. 19, no. 4, pp. 107-117, 2002.
-
(2002)
IEEE Design & Test of Computers
, vol.19
, Issue.4
, pp. 107-117
-
-
Kondratyev, A.1
Lwin, K.2
-
59
-
-
77957956590
-
Testing of asynchronous designs by inappropriate means, synchronous approach
-
April
-
A. Kondratyev, L. Sorensen, and A. Streich, "Testing of asynchronous designs by inappropriate means, synchronous approach," in Proc. International Symposium on Advanced Research in Asynchronous Circuits and Systems, pp. 171-180, April 2002.
-
(2002)
Proc. International Symposium on Advanced Research in Asynchronous Circuits and Systems
, pp. 171-180
-
-
Kondratyev, A.1
Sorensen, L.2
Streich, A.3
-
62
-
-
28444483942
-
Delay insensitive encoding and power analysis: A balancing act
-
K. J. Kulikowski, M. Su, A. Smirnov, A. Taubin, M. G. Karpovsky, and D. MacDonald, "Delay insensitive encoding and power analysis: A balancing act," in Proc. International Symposium on Advanced Research in Asynchronous Circuits and Systems, pp. 116-125, 2005.
-
(2005)
Proc. International Symposium on Advanced Research in Asynchronous Circuits and Systems
, pp. 116-125
-
-
Kulikowski, K.J.1
Su, M.2
Smirnov, A.3
Taubin, A.4
Karpovsky, M.G.5
MacDonald, D.6
-
63
-
-
0026623575
-
Test pattern generation using boolean satisfiability
-
T. Larrabee, "Test pattern generation using boolean satisfiability," IEEE Transactions on Computer-Aided Design, vol. 11, no. 1, pp. 4-15, 1992.
-
(1992)
IEEE Transactions on Computer-Aided Design
, vol.11
, Issue.1
, pp. 4-15
-
-
Larrabee, T.1
-
64
-
-
34548735583
-
Asynchronous control circuits
-
Kluwer Academic Publishers
-
L. Lavagno and S. M. Nowick, "Asynchronous control circuits," in Logic Synthesis and Verification, pp. 255-284, Kluwer Academic Publishers, 2002.
-
(2002)
Logic Synthesis and Verification
, pp. 255-284
-
-
Lavagno, L.1
Nowick, S.M.2
-
65
-
-
0042882274
-
Polychrony for system design
-
April
-
P. Le Guernic, J.-P. Talpin, and J.-C. L. Lann, "Polychrony for system design," Journal of Circuits, Systems and Computers, April 2003.
-
(2003)
Journal of Circuits, Systems and Computers
-
-
Le Guernic, P.1
Talpin, J.-P.2
Lann, J.-C.L.3
-
67
-
-
34548765643
-
-
Liberty CCS: www.synopsys.com/products/libertyccs/libertyccs.html.
-
-
-
Liberty, C.C.S.1
-
68
-
-
77957975766
-
Asynchronous design using commercial HDL synthesis tools
-
IEEE Computer Society Press, April
-
M. Ligthart, K. Fant, R. Smith, A. Taubin, and A. Kondratyev, "Asynchronous design using commercial HDL synthesis tools," in Proc. International Symposium on Advanced Research in Asynchronous Circuits and Systems, pp. 114-125, IEEE Computer Society Press, April 2000.
-
(2000)
Proc. International Symposium on Advanced Research in Asynchronous Circuits and Systems
, pp. 114-125
-
-
Ligthart, M.1
Fant, K.2
Smith, R.3
Taubin, A.4
Kondratyev, A.5
-
70
-
-
0030244752
-
Phased logic: Supporting the synchronous design paradigm with delay-insensitive circuitry
-
September
-
D. H. Linder and J. C. Harden, "Phased logic: Supporting the synchronous design paradigm with delay-insensitive circuitry," IEEE Transactions on Computers, vol. 45, no. 9, pp. 1031-1044, September 1996.
-
(1996)
IEEE Transactions on Computers
, vol.45
, Issue.9
, pp. 1031-1044
-
-
Linder, D.H.1
Harden, J.C.2
-
71
-
-
34548765093
-
-
A. Lines, Pipelined Asynchronous Circuits. PhD thesis, California Institute of Technology, 1998. (CaltechCSTR:1998.cs-tr-95-21).
-
A. Lines, Pipelined Asynchronous Circuits. PhD thesis, California Institute of Technology, 1998. (CaltechCSTR:1998.cs-tr-95-21).
-
-
-
-
72
-
-
84881243015
-
Nexus: An asynchronous crossbar interconnect for synchronous system-on-chip designs
-
August
-
A. Lines, "Nexus: An asynchronous crossbar interconnect for synchronous system-on-chip designs," in Proceedings of the 11th Symposium on High Performance Interconnects, pp. 2-9, August 2003.
-
(2003)
Proceedings of the 11th Symposium on High Performance Interconnects
, pp. 2-9
-
-
Lines, A.1
-
73
-
-
34548736702
-
-
MS Thesis. A Balanced-Power Domino-Style Standard Cell Library for Fine-Grain Asynchronous Pipelined Design to Resist Differential Power Analysis Attacks. PhD thesis, Boston University
-
D. J. MacDonald, MS Thesis. A Balanced-Power Domino-Style Standard Cell Library for Fine-Grain Asynchronous Pipelined Design to Resist Differential Power Analysis Attacks. PhD thesis, Boston University, 2005.
-
(2005)
-
-
MacDonald, D.J.1
-
74
-
-
84957580817
-
Slack elasticity in concurrent computing
-
J. Jeuring, ed, pp
-
R. Manohar and A. J. Martin, "Slack elasticity in concurrent computing," in Proc. 4th International Conference on the Mathematics of Program Construction, (J. Jeuring, ed.), pp. 272-285, 1998.
-
(1998)
Proc. 4th International Conference on the Mathematics of Program Construction
, pp. 272-285
-
-
Manohar, R.1
Martin, A.J.2
-
75
-
-
0002927123
-
Programming in VLSI: From communicating processes to delayinsensitive circuits
-
Developments in Concurrency and Communication, C. A. R. Hoare, ed, AddisonWesley
-
A. J. Martin, "Programming in VLSI: From communicating processes to delayinsensitive circuits," in Developments in Concurrency and Communication, (C. A. R. Hoare, ed.). UT Year of Programming Series, pp. 1-64, AddisonWesley, 1990.
-
(1990)
UT Year of Programming Series
, pp. 1-64
-
-
Martin, A.J.1
-
76
-
-
0022879965
-
Compiling communicating processes into delay-insensitive VLSI circuits
-
A. J. Martin, "Compiling communicating processes into delay-insensitive VLSI circuits," Distributed Computing, vol. 1, no. 4, pp. 226-234, 1986.
-
(1986)
Distributed Computing
, vol.1
, Issue.4
, pp. 226-234
-
-
Martin, A.J.1
-
77
-
-
0001337809
-
The limitations to delay-insensitivity in asynchronous circuits
-
W. J. Dally, ed, pp, MIT Press
-
A. J. Martin, "The limitations to delay-insensitivity in asynchronous circuits," in Advanced Research in VLSI, (W. J. Dally, ed.), pp. 263-278, MIT Press, 1990.
-
(1990)
Advanced Research in VLSI
, pp. 263-278
-
-
Martin, A.J.1
-
78
-
-
0040383388
-
Testing delay-insensitive circuits
-
C. H. Séquin, ed, pp, MIT Press
-
A. J. Martin and P. J. Hazewindus, "Testing delay-insensitive circuits," in Advanced Research in VLSI, (C. H. Séquin, ed.), pp. 118-132, MIT Press, 1991.
-
(1991)
Advanced Research in VLSI
, pp. 118-132
-
-
Martin, A.J.1
Hazewindus, P.J.2
-
79
-
-
0031364001
-
The design of an asynchronous MIPS R.3000 microprocessor
-
September
-
A. J. Martin, A. Lines, R. Manohar, M. Nyström, P. Pénzes, R. Southworth, and U. Cummings, "The design of an asynchronous MIPS R.3000 microprocessor," in Advanced Research in VLSI, pp. 164-181, September 1997.
-
(1997)
Advanced Research in VLSI
, pp. 164-181
-
-
Martin, A.J.1
Lines, A.2
Manohar, R.3
Nyström, M.4
Pénzes, P.5
Southworth, R.6
Cummings, U.7
-
80
-
-
77957951589
-
The lutonium: A sub-nanojoule asynchronous 8051 microcontroller
-
IEEE Computer Society Press, May
-
A. J. Martin, M. Nyström, K. Papadantonakis, P. I. Pénzes, P. Prakash, C. G. Wong, J. Chang, K. S. Ko, B. Lee, E. Ou, J. Pugh, E.-V. Talvala, J. T. Tong, and A. Tura, "The lutonium: A sub-nanojoule asynchronous 8051 microcontroller," in Proc. International Symposium on Advanced Research in Asynchronous Circuits and Systems, pp. 14-23, IEEE Computer Society Press, May 2003.
-
(2003)
Proc. International Symposium on Advanced Research in Asynchronous Circuits and Systems
, pp. 14-23
-
-
Martin, A.J.1
Nyström, M.2
Papadantonakis, K.3
Pénzes, P.I.4
Prakash, P.5
Wong, C.G.6
Chang, J.7
Ko, K.S.8
Lee, B.9
Ou, E.10
Pugh, J.11
Talvala, E.-V.12
Tong, J.T.13
Tura, A.14
-
81
-
-
33947432403
-
Asynchronous techniques for system-onchip design
-
June
-
J. Martin Alain and M. Nystrom, "Asynchronous techniques for system-onchip design," Proceedings of the IEEE, vol. 94, no. 6, pp. 1089-1120, June 2006.
-
(2006)
Proceedings of the IEEE
, vol.94
, Issue.6
, pp. 1089-1120
-
-
Martin Alain, J.1
Nystrom, M.2
-
82
-
-
0009753213
-
Measuring an asynchronous processor's power and noise
-
J. McCardle and D. Chester, "Measuring an asynchronous processor's power and noise," in SNUG, 2001.
-
(2001)
SNUG
-
-
McCardle, J.1
Chester, D.2
-
83
-
-
0030679277
-
A FIFO ring oscillator performance experiment
-
IEEE Computer Society Press, April
-
C. E. Moinar, I. W. Jones, B. Coates, and J. Lexau, "A FIFO ring oscillator performance experiment," in Proc. International Symposium on Advanced Research in Asynchronous Circuits and Systems, pp. 279-289, IEEE Computer Society Press, April 1997.
-
(1997)
Proc. International Symposium on Advanced Research in Asynchronous Circuits and Systems
, pp. 279-289
-
-
Moinar, C.E.1
Jones, I.W.2
Coates, B.3
Lexau, J.4
-
84
-
-
0041325255
-
Balanced self-checking asynchronous logic for smart card applications
-
October
-
S. Moore, R. Anderson, R. Mullins, G. Taylor, and J. J. A. Fournier, "Balanced self-checking asynchronous logic for smart card applications," Microprocessors and Microsystems, vol. 27, no. 9, pp. 421-430, October 2003.
-
(2003)
Microprocessors and Microsystems
, vol.27
, Issue.9
, pp. 421-430
-
-
Moore, S.1
Anderson, R.2
Mullins, R.3
Taylor, G.4
Fournier, J.J.A.5
-
85
-
-
0034852165
-
Chaff: Engineering an efficient SAT solver
-
M. Moskewicz, C. Madigan, Y. Zhao, L. Zhang, and S. Malik, "Chaff: Engineering an efficient SAT solver," in Proc. ACM/IEEE Design Automation Conference, 2001.
-
(2001)
Proc. ACM/IEEE Design Automation Conference
-
-
Moskewicz, M.1
Madigan, C.2
Zhao, Y.3
Zhang, L.4
Malik, S.5
-
87
-
-
0024645936
-
Petri nets: Properties, analysis and applications
-
April
-
T. Murata, "Petri nets: Properties, analysis and applications," Proceedings of the IEEE, vol. 77, no. 4, pp. 541-574, April 1989.
-
(1989)
Proceedings of the IEEE
, vol.77
, Issue.4
, pp. 541-574
-
-
Murata, T.1
-
90
-
-
33749622756
-
An ultra-low energy asynchronous processor for wireless sensor networks
-
March
-
L. Necchi, L. Lavagno, D. Pandini, and L. Vanzago, "An ultra-low energy asynchronous processor for wireless sensor networks," in Proc. International Symposium on Advanced Research in Asynchronous Circuits and Systems, pp. 78-85, March 2006.
-
(2006)
Proc. International Symposium on Advanced Research in Asynchronous Circuits and Systems
, pp. 78-85
-
-
Necchi, L.1
Lavagno, L.2
Pandini, D.3
Vanzago, L.4
-
93
-
-
57849107875
-
The future of computer architecture
-
D. Patterson, "The future of computer architecture, berkeley eecs annual research symposium 2006, http://www.eecs.berkeley.edu/BEARS/ presentations/06Patterson.ppt," 2006.
-
(2006)
berkeley eecs annual research symposium
-
-
Patterson, D.1
-
94
-
-
26444558132
-
Implementation of handshake components
-
Comunicating Sequential Processes, the First 25 Years, of, A. E. Abdallah, C. B. Jones, and J. W. Sanders, eds, pp
-
A. Peeters, "Implementation of handshake components," in Comunicating Sequential Processes, the First 25 Years, Volume 3525 of Lecture Notes in Computer Science, (A. E. Abdallah, C. B. Jones, and J. W. Sanders, eds.), pp. 98-132, 2005.
-
(2005)
Lecture Notes in Computer Science
, vol.3525
, pp. 98-132
-
-
Peeters, A.1
-
97
-
-
0037395867
-
Laying out circuits on asynchronous cellular arrays: A step towards feasible nanocomputers?
-
F. Peper, J. Lee, S. Adachi, and S. Mashiko, "Laying out circuits on asynchronous cellular arrays: A step towards feasible nanocomputers?," Nanotechnology, vol. 14, pp. 469-485, 2003.
-
(2003)
Nanotechnology
, vol.14
, pp. 469-485
-
-
Peper, F.1
Lee, J.2
Adachi, S.3
Mashiko, S.4
-
99
-
-
77957956814
-
SPA -A synthesisable amulet core for smartcard applications
-
April
-
L. A. Plana, P. A. Riocreux, W. J. Bainbridge, A. Bardsley, J. D. Garside, and S. Temple, "SPA -A synthesisable amulet core for smartcard applications," in Proc. International Symposium on Advanced Research in Asynchronous Circuits and Systems, pp. 201-210, April 2002.
-
(2002)
Proc. International Symposium on Advanced Research in Asynchronous Circuits and Systems
, pp. 201-210
-
-
Plana, L.A.1
Riocreux, P.A.2
Bainbridge, W.J.3
Bardsley, A.4
Garside, J.D.5
Temple, S.6
-
103
-
-
3042647218
-
A design framework for asynchronous/synchronous circuits based on CHP to HDL translation
-
April
-
M. Renaudin, P. Vivet, and F. Robin, "A design framework for asynchronous/synchronous circuits based on CHP to HDL translation," in Proc. International Symposium on Advanced Research in Asynchronous Circuits and Systems, pp. 135-144, April 1999.
-
(1999)
Proc. International Symposium on Advanced Research in Asynchronous Circuits and Systems
, pp. 135-144
-
-
Renaudin, M.1
Vivet, P.2
Robin, F.3
-
104
-
-
5544276785
-
Linear test times for delay-insensitive circuits: A compilation strategy
-
S. Furber and M. Edwards, eds, pp, Elsevier Science Publishers
-
M. Roncken and R. Saeijs, "Linear test times for delay-insensitive circuits: A compilation strategy," in Asynchronous Design Methodologies, (S. Furber and M. Edwards, eds.), pp. 13-27, Elsevier Science Publishers, 1993.
-
(1993)
Asynchronous Design Methodologies
, pp. 13-27
-
-
Roncken, M.1
Saeijs, R.2
-
105
-
-
0033080339
-
Defect-oriented testability for asynchronous ICs
-
February
-
M. Roncken, "Defect-oriented testability for asynchronous ICs," Proceedings of the IEEE, vol. 87, no. 2, pp. 363-375, February 1999.
-
(1999)
Proceedings of the IEEE
, vol.87
, Issue.2
, pp. 363-375
-
-
Roncken, M.1
-
106
-
-
0022216284
-
Signal graphs: From self-timed to timed ones
-
Torino, Italy, pp, IEEE Computer Society Press, July
-
L. Y. Rosenblum and A. V. Yakovlev, "Signal graphs: From self-timed to timed ones," in Proceedings of International Workshop on Timed Petri Nets, (Torino, Italy), pp. 199-207, IEEE Computer Society Press, July 1985.
-
(1985)
Proceedings of International Workshop on Timed Petri Nets
, pp. 199-207
-
-
Rosenblum, L.Y.1
Yakovlev, A.V.2
-
107
-
-
33750915626
-
RAPPID: An asynchronous instruction length decoder
-
April
-
S. Rotem, K. Stevens, R. Ginosar, P. Beerel, C. Myers, K. Yun, R. Kol, C. Dike, M. Roncken, and B. Agapiev, "RAPPID: An asynchronous instruction length decoder," in Proc. International Symposium on Advanced Research in Asynchronous Circuits and Systems, pp. 60-70, April 1999.
-
(1999)
Proc. International Symposium on Advanced Research in Asynchronous Circuits and Systems
, pp. 60-70
-
-
Rotem, S.1
Stevens, K.2
Ginosar, R.3
Beerel, P.4
Myers, C.5
Yun, K.6
Kol, R.7
Dike, C.8
Roncken, M.9
Agapiev, B.10
-
108
-
-
33746333289
-
High Level modeling of channel-based asynchronous circuits using verilog
-
J. F. Broenink et al, ed, pp, IOS Press, September
-
A. Saifhashemi and P. A. Beerel, "High Level modeling of channel-based asynchronous circuits using verilog," in Communicating Process Architectures, (J. F. Broenink et al., ed.), pp. 275-288, IOS Press, September 2005.
-
(2005)
Communicating Process Architectures
, pp. 275-288
-
-
Saifhashemi, A.1
Beerel, P.A.2
-
109
-
-
0041633864
-
Verilog HDL, powered by PLI: A suitable framework for describing and modeling asynchronous circuits at all levels of abstraction
-
June
-
A. Saifhashemi and H. Pedram, "Verilog HDL, powered by PLI: A suitable framework for describing and modeling asynchronous circuits at all levels of abstraction," in Proc. ACM/IEEE Design Automation Conference, pp. 330-333, June 2003.
-
(2003)
Proc. ACM/IEEE Design Automation Conference
, pp. 330-333
-
-
Saifhashemi, A.1
Pedram, H.2
-
110
-
-
34548711423
-
-
Savant Project-http://www.cliftonlabs.com/savantp.htm.
-
Savant Project
-
-
-
111
-
-
0001951703
-
System timing
-
C. A. Mead and L. A. Conway, eds, ch. 7, Addison-Wesley
-
C. L. Seitz, "System timing," in Introduction to VLSI Systems, (C. A. Mead and L. A. Conway, eds.), ch. 7, Addison-Wesley, 1980.
-
(1980)
Introduction to VLSI Systems
-
-
Seitz, C.L.1
-
114
-
-
77957931942
-
An adaptively-pipelined mixed synchronous-asynchronous digital FIR- filter chip operating at 1.3 gigahertz
-
April
-
M. Singh, J. A. Tierno, A. Rylyakov, S. Rylov, and S. M. Nowick, "An adaptively-pipelined mixed synchronous-asynchronous digital FIR- filter chip operating at 1.3 gigahertz," in Proc. International Symposium on Advanced Research in Asynchronous Circuits and Systems, pp. 84-95, April 2002.
-
(2002)
Proc. International Symposium on Advanced Research in Asynchronous Circuits and Systems
, pp. 84-95
-
-
Singh, M.1
Tierno, J.A.2
Rylyakov, A.3
Rylov, S.4
Nowick, S.M.5
-
115
-
-
85010424421
-
Synthesizing asynchronous micropipelines with design compiler
-
Boston
-
A. Smirnov and A. Taubin, "Synthesizing asynchronous micropipelines with design compiler," in Synopsys Users Group, Boston, 2006.
-
(2006)
Synopsys Users Group
-
-
Smirnov, A.1
Taubin, A.2
-
117
-
-
33746238162
-
An automated fine-grain pipelining using domino style asynchronous library
-
St.Malo, France, IEEE CS Press
-
A. Smirnov, A. Taubin, and M. Karpovsky, "An automated fine-grain pipelining using domino style asynchronous library," in ACSD 2005: Fifth International Conference on Application of Concurrency to System Design, (St.Malo, France), IEEE CS Press, 2005.
-
(2005)
ACSD 2005: Fifth International Conference on Application of Concurrency to System Design
-
-
Smirnov, A.1
Taubin, A.2
Karpovsky, M.3
-
118
-
-
33746250583
-
Gate transfer level synthesis as an automated approach to fine-grain pipelining
-
Bologna, Italy
-
A. Smirnov, A. Taubin, M. Karpovsky, and L. Rozenblyum, "Gate transfer level synthesis as an automated approach to fine-grain pipelining," in Workshop on Token Based Computing (ToBaCo), (Bologna, Italy), 2004.
-
(2004)
Workshop on Token Based Computing (ToBaCo)
-
-
Smirnov, A.1
Taubin, A.2
Karpovsky, M.3
Rozenblyum, L.4
-
120
-
-
17644364039
-
Design and analysis of dual-rail circuits for security applications
-
April
-
D. Sokolov, J. Murphy, A. Bystrov, and A. Yakovlev, "Design and analysis of dual-rail circuits for security applications," IEEE Transactions on Computers, vol. 54, no. 4, pp. 449-460, April 2005.
-
(2005)
IEEE Transactions on Computers
, vol.54
, Issue.4
, pp. 449-460
-
-
Sokolov, D.1
Murphy, J.2
Bystrov, A.3
Yakovlev, A.4
-
122
-
-
0027677633
-
Delay-insensitive multi-ring structures
-
October
-
J. Sparsø and J. Staunstrup, "Delay-insensitive multi-ring structures," Integration, the VLSI Journal, vol. 15, no. 3, pp. 313-340, October 1993.
-
(1993)
Integration, the VLSI Journal
, vol.15
, Issue.3
, pp. 313-340
-
-
Sparsø, J.1
Staunstrup, J.2
-
123
-
-
85008025338
-
-
Special issue on asynchronous circuits and systems. Proceedings of the IEEE, 87, no. 2, pp. 1-375, February 1999.
-
Special issue on asynchronous circuits and systems. Proceedings of the IEEE, vol. 87, no. 2, pp. 1-375, February 1999.
-
-
-
-
125
-
-
0024683698
-
Micropipelines
-
June
-
I. E. Sutherland, "Micropipelines," Communications of the ACM, vol. 32, no. 6, pp. 720-738, June 1989.
-
(1989)
Communications of the ACM
, vol.32
, Issue.6
, pp. 720-738
-
-
Sutherland, I.E.1
-
127
-
-
0041975086
-
Synchronous full-scan for asynchronous handshake circuits
-
F. te Beest, A. Peeters, K. van Berkel, and H. Kerkhoff, "Synchronous full-scan for asynchronous handshake circuits," Journal of Electronic Testing: Theory and Applications, vol. 19, pp. 397-406, 2003.
-
(2003)
Journal of Electronic Testing: Theory and Applications
, vol.19
, pp. 397-406
-
-
te Beest, F.1
Peeters, A.2
van Berkel, K.3
Kerkhoff, H.4
-
128
-
-
0036113496
-
A 1.3 GSample/s 10-tap full-rate variable-latency selftimed FIR filter with clocked interfaces
-
February
-
J. Tierno, A. Rylyakov, S. Rylov, M. Singh, P. Ampadu, S. Nowick, M. Immediato, and S. Gowda, "A 1.3 GSample/s 10-tap full-rate variable-latency selftimed FIR filter with clocked interfaces," in International Solid State Circuits Conference, February 2002.
-
(2002)
International Solid State Circuits Conference
-
-
Tierno, J.1
Rylyakov, A.2
Rylov, S.3
Singh, M.4
Ampadu, P.5
Nowick, S.6
Immediato, M.7
Gowda, S.8
-
129
-
-
84893732023
-
A dynamic and differential cmos logic with signal independent power consumption to withstand differential power analysis on smart cards
-
K. Tiri, M. Akmal, and I. Verbauwhede, "A dynamic and differential cmos logic with signal independent power consumption to withstand differential power analysis on smart cards," in 28th European Solid-State Circuits Conference (ESSCIRC 2002), 2002.
-
(2002)
28th European Solid-State Circuits Conference (ESSCIRC 2002)
-
-
Tiri, K.1
Akmal, M.2
Verbauwhede, I.3
-
130
-
-
27244438768
-
Prototype IC with wddl and differential routing -dpa sesistance assessment
-
Edinburgh, pp, LNCS3659, Springer
-
K. Tiri, W. Hwang, A. Hodjat, L. Bo-Cheng, Y. Shenglin, P. Schaumont, and I. Verbauwhede, "Prototype IC with wddl and differential routing -dpa sesistance assessment," in Chyptographic Hardware and Embedded Systems - CHES, (Edinburgh), pp. 354-365, LNCS3659, Springer, 2005.
-
(2005)
Chyptographic Hardware and Embedded Systems - CHES
, pp. 354-365
-
-
Tiri, K.1
Hwang, W.2
Hodjat, A.3
Bo-Cheng, L.4
Shenglin, Y.5
Schaumont, P.6
Verbauwhede, I.7
-
133
-
-
34548720001
-
-
TSMC 0.18mm Process 1.8-Volt SAGE-X TM Standard Cell Library Databook. September 2003.
-
TSMC 0.18mm Process 1.8-Volt SAGE-X TM Standard Cell Library Databook. September 2003.
-
-
-
-
134
-
-
0003270928
-
Handshake Circuits: An Asynchronous Architecture for VLSI Programming
-
of, Cambridge University Press
-
K. van Berkel, Handshake Circuits: An Asynchronous Architecture for VLSI Programming. Vol. 5 of International Series on Parallel Computation, Cambridge University Press, 1993.
-
(1993)
International Series on Parallel Computation
, vol.5
-
-
van Berkel, K.1
-
136
-
-
0029221856
-
Stretching quasi delay insensitivity by means of extended isochronic forks
-
IEEE Computer Society Press, May
-
K. van Berkel, F. Huberts, and A. Peeters, "Stretching quasi delay insensitivity by means of extended isochronic forks," in Asynchronous Design Methodologies, pp. 99-106, IEEE Computer Society Press, May 1995.
-
(1995)
Asynchronous Design Methodologies
, pp. 99-106
-
-
van Berkel, K.1
Huberts, F.2
Peeters, A.3
-
137
-
-
0041882135
-
Adding synchronous and LSSD modes to asynchronous circuits
-
October
-
K. van Berkel, A. Peeters, and F. te Beest, "Adding synchronous and LSSD modes to asynchronous circuits," Microprocessors and Microsystems, vol. 27, no. 9, pp. 461-471, October 2003.
-
(2003)
Microprocessors and Microsystems
, vol.27
, Issue.9
, pp. 461-471
-
-
van Berkel, K.1
Peeters, A.2
te Beest, F.3
-
138
-
-
84974715759
-
-
V. Varshavsky, V. Marakhovsky, and T.-A. Chu, Logical timing (global synchronization of asynchronous arrays, in The First International Symposium on Parallel Algorithm/Architecture Synthesis, (Aizu-Wakamatsu, Japan), pp. 130-138, March 1995.
-
V. Varshavsky, V. Marakhovsky, and T.-A. Chu, "Logical timing (global synchronization of asynchronous arrays," in The First International Symposium on Parallel Algorithm/Architecture Synthesis, (Aizu-Wakamatsu, Japan), pp. 130-138, March 1995.
-
-
-
-
139
-
-
0004077665
-
-
V. I. Varshavsky, ed, Dordrecht, The Netherlands, Kluwer Academic Publishers
-
V. I. Varshavsky, ed., Self-Timed Control of Concurrent Processes: The Design of Aperiodic Logical Circuits in Computers and Discrete Systems, (Dordrecht, The Netherlands), Kluwer Academic Publishers, 1990.
-
(1990)
Self-Timed Control of Concurrent Processes: The Design of Aperiodic Logical Circuits in Computers and Discrete Systems
-
-
-
140
-
-
33646429255
-
Hardware compilation of application-specific memory-access interconnect
-
G. Venkataramani, T. Bjerregaard, T. Chelcea, and S. C. Goldstein, "Hardware compilation of application-specific memory-access interconnect," IEEE Trans. on CAD of Integrated Circuits and Systems, vol. 25, no. 5, pp. 756-771, 2006.
-
(2006)
IEEE Trans. on CAD of Integrated Circuits and Systems
, vol.25
, Issue.5
, pp. 756-771
-
-
Venkataramani, G.1
Bjerregaard, T.2
Chelcea, T.3
Goldstein, S.C.4
-
141
-
-
12344330497
-
C to asynchronous dataflow circuits: An end-to-end toolflow
-
Temecula, CA, June
-
G. Venkataramani, M. Budiu, T. Chelcea, and S. Goldstein, "C to asynchronous dataflow circuits: An end-to-end toolflow," in IWLS, pp. 501-508, Temecula, CA, June 2004.
-
(2004)
IWLS
, pp. 501-508
-
-
Venkataramani, G.1
Budiu, M.2
Chelcea, T.3
Goldstein, S.4
-
142
-
-
39749194704
-
Leveraging protocol knowledge in slack matching
-
San Jose, CA, USA, November
-
G. Venkataramani and S. Copen Goldstein, "Leveraging protocol knowledge in slack matching," in IEEE/ACM International Conference on Computer-Aided Design, (San Jose, CA, USA), November 2006.
-
(2006)
IEEE/ACM International Conference on Computer-Aided Design
-
-
Venkataramani, G.1
Copen Goldstein, S.2
-
143
-
-
0002391456
-
Delay-insensitive codes-an overview
-
T. Verhoeff, "Delay-insensitive codes-an overview," Distributed Computing, vol. 3, no. 1, pp. 1-8, 1988.
-
(1988)
Distributed Computing
, vol.3
, Issue.1
, pp. 1-8
-
-
Verhoeff, T.1
-
145
-
-
38049063843
-
Cost-aware synthesis of asynchronous circuits based on partial acknowledgement
-
IEEE Computer Society Press, November
-
Y. Zhou, D. Sokolov, and A. Yakovlev, "Cost-aware synthesis of asynchronous circuits based on partial acknowledgement," in Proc. International Conf. Computer-Aided Design (ICCAD), pp. 255-260, IEEE Computer Society Press, November 2006.
-
(2006)
Proc. International Conf. Computer-Aided Design (ICCAD)
, pp. 255-260
-
-
Zhou, Y.1
Sokolov, D.2
Yakovlev, A.3
|