A re-configurable FTL (Flash Translation Layer) architecture for NAND flash based applications

Proceedings of the International Workshop on Rapid System Prototyping

Volumn , Issue , 2007, Pages 202-208

  Park, Chanik ^a   Cheon, Wonmoon ^a   Lee, Yangsup ^a   Jung, Myoung Soo ^a   Cho, Wonhee ^a   Yoon, Hanbin ^a  

^a SAMSUNG Electronics   (South Korea)

Author keywords

[No Author keywords available]

Indexed keywords

ALGORITHMS; COMPUTER ARCHITECTURE; CONFORMAL MAPPING; LOGIC GATES; PARAMETER ESTIMATION;

MP3 PLAYERS; NAND FLASH APPLICATION; SOLID-STATE DISK;

FLASH MEMORY;

EID: 34548724459     PISSN: 10746005     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/RSP.2007.8     Document Type: Conference Paper

References (6)

1. Jesung Kim, JongMin Kim, Sam H. Noh, Sang Lyul Min and Yookun Cho, "A Space-Efficient Flash Translation Layer for CompactFlash Systems", IEEE Transactions on Consumer Electronics, Vol. 48, No. 2, May 2002.
2. Samsung Electronics, "NAND Flash Memory & SmartMedia Databook", 2005.
3. Eran Gal and Sivan Toledo. Algorithms and data structures for flash memories. ACM Computing Surveys, 37(2), 2005.
4. S.-W. Lee, D.-J. Park, T.-S Chung, D.-H. Lee, S. -W. Park, and H.-J. Song, FAST:An FTL Scheme with Fully Associative Sector Translations, UKC 2005, Aug., 2005.
5. Chang, L. P. and Kuo, T. W. An efficient management scheme for large scale flash memory storage systems. In proceedings of the ACM Symposium on Applied Computing (SAC), Mar., ACM, New York, 862-868.
6. http://www.sysinternals.com/Utilities/Diskmon.html