Optimizing the fast fourier transform on a multi-core architecture

Proceedings - 21st International Parallel and Distributed Processing Symposium, IPDPS 2007; Abstracts and CD-ROM

Volumn , Issue , 2007, Pages

  Chen, Long ^a   Hu, Ziang ^a   Lin, Junmin ^b   Gao, Guang R ^a  

^a UNIVERSITY OF DELAWARE   (United States)

^b TSINGHUA UNIVERSITY   (China)

Author keywords

[No Author keywords available]

Indexed keywords

COMPUTER ARCHITECTURE; DATA STORAGE EQUIPMENT; FEEDBACK; MICROPROCESSOR CHIPS; OPTIMIZATION; PROGRAM COMPILERS; SOFTWARE DESIGN;

APPLICATION DEVELOPERS; LARGE REGISTER FILES; MICROPROCESSOR CHIP ARCHITECTURES; MULTI CORE ARCHITECTURES; SYSTEM SOFTWARE DESIGNERS;

FAST FOURIER TRANSFORMS;

EID: 34548712562     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/IPDPS.2007.370639     Document Type: Conference Paper

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