A low jitter, low power, cmos 1.25-3.125gbps transceiver

European Solid-State Circuits Conference

Volumn , Issue , 2001, Pages 121-124

  Younis, Ahmed ^a   Boecker, Charlie ^a   Hossain, Kazi ^a   Abughazaleh, Firas ^a   Das, Bodhi ^a   Chen, Yiqin ^a   Robinson, Moises ^a   Irwin, Scott ^a   Grung, Bernie ^a  

^a XILINX INC   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

CMOS TRANSCEIVERS; DETERMINISTIC JITTERS; DIGITAL PROCESS; FULL-DUPLEX; JITTER TOLERANCE; POWER SUPPLY; RANDOM JITTERS; SERIALIZER/DESERIALIZER;

CLOCK AND DATA RECOVERY CIRCUITS (CDR CIRCUITS);

TIMING JITTER;

EID: 34548485955     PISSN: 19308833     EISSN: None     Source Type: Journal    
DOI: None     Document Type: Article

References (4)

1. A. Fiedier, R. Mactaggart, J. Welch, and S. Krishnan, "A 1.0625Gbps Transceiver with 2x-Oversampling and Transmit Signal Pre-Emphasis", ISSCC Digest of Technical Papers, FP15.1, Feb. 1997.
2. R. Gu, J.M. Tran, H.-C. Lin, A.-L. Yee, and M. Izzard, " A 0.5-3.5Gb/s Low-Power Low-Jitter Serial Data CMOS Transceiver", ISSCC Digest of Technical Papers, WA20.4, Feb. 1999.
3. U.S. Patent Application entitled "Phase Lock loop and Transconductance Circuit for Clock Recovery", submitted Dec. 19, 1999.
4. P. Larsson, "Parasitic Resistance in an MOS Transistor Used as On-Chip Decoupling Capacitance", IEEE Journal of Solid-State Circuits, Vol. 32, April 1997.